Steven H Magee

US Patent:

6598007, Jul 22, 2003

Filed:

Jan 5, 2001

Appl. No.:

09/755427

Inventors:

Frank J. Moizio - Dallas TX
Steven R. Magee - Carrollton TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G01P 300

US Classification:

702145, 702 79, 702148

Abstract:

Asynchronous position pulses drive an interrupt to store pulse times via direct memory access; then synchronous sampling and analysis of the stored position pulse timings provides rate detection useful for feedback as useful in motor control.

US Patent:

6801922, Oct 5, 2004

Filed:

Jun 4, 2001

Appl. No.:

09/873592

Inventors:

Cynthia P. Goszewski - Dallas TX
Steven R. Magee - Carrollton TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1710

US Classification:

708313, 341 61

Abstract:

Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated by interpolation from a table of oversampled values with the oversampling rate lower for outlying lobes of the impulse response.

US Patent:

61051195, Aug 15, 2000

Filed:

Apr 4, 1997

Appl. No.:

8/833153

Inventors:

Jeffrey L. Kerr - Garland TX
John Ling Wing So - Plano TX
Steven R. Magee - Carrollton TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1200

US Classification:

711219

Abstract:

An integrated circuit (1720) includes a dual-port memory (3330. 1) having a first memory port (Port A) and a second memory port (Port B), a bus interface block (5010) including bus master (5016) and bus slave circuitry (5018), and a byte-channeling block (5310) coupled between the first memory port (Port A) and the bus interface block (5010) operable to convert non-aligned data addresses into aligned data. Advantageously, this invention includes a single bus master serving all application hardware. This relieves the host of the extra burden of communicating to slave circuits, reducing host I/O MIPS significantly. The digital signal processor with an ASIC wrapper of this invention together provide super-bus-mastering to access the entire memory space in the system, including the entire virtual memory space accessible by the host processor. Other processes, systems, devices and methods are also disclosed.

US Patent:

61794899, Jan 30, 2001

Filed:

Apr 4, 1997

Appl. No.:

8/833267

Inventors:

John Ling Wing So - Plano TX
Jeffrey L. Kerr - Garland TX
Steven R. Magee - Carrollton TX
Jun Tang - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1300

US Classification:

395672

Abstract:

A process is provided for operating a computer system (100) having a storage holding an operating system (OS) and an application program (APP. exe) and a third program (VSP Kernel), a first processor (106) having an instruction set, and a second processor (1730) having a different instruction set. The process includes a first step of running the first processor (106) to determine whether a part of the application shall be run on the first processor or the second processor and then establishing a second processor object (VSP OBJECT1) if said part shall be run on the second processor and the first processor (106) sending a message that the second processor (1730) is to run said at least part of the application program. The third program establishes message handling functions and bus masters data transfer operations for the second processor between the host running the operating system and the second processor running the third program. The process concurrently runs the second processor to perform operations defined by the third program, including to access memory to detect the message that the second processor is to run said at least part of the application program, and runs the second processor (1730) to access the second processor object and thereby determine operations for the second processor to access second processor instructions for said part of the application program and data to be processed according to said second processor instructions.