Steven Dwayne Marshall

US Patent:

50329863, Jul 16, 1991

Filed:

Sep 22, 1989

Appl. No.:

7/411180

Inventors:

Bimal Pathak - Stafford TX
Steven P. Marshall - Missouri City TX
James F. Potts - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1206

US Classification:

364200

Abstract:

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/subtractor in the auxiliary arithmetic logic units either adds or substracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register.

US Patent:

49087487, Mar 13, 1990

Filed:

Jul 28, 1987

Appl. No.:

7/078350

Inventors:

Bimal Pathak - Stafford TX
Steven P. Marshall - Missouri City TX
James F. Potts - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 500

US Classification:

364200

Abstract:

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/substractor in the auxiliary arithmetic logic units either adds or subtracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register.