Steven Joseph Marshall

US Patent:

7710969, May 4, 2010

Filed:

May 15, 2006

Appl. No.:

11/383330

Inventors:

Andre Szczepanek - Hartwell, GB
Martin Yu Li - Missouri City TX, US
Steven P. Marshall - Houston TX, US
Travis M. Scheckel - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L 12/28

US Classification:

370392, 370351

Abstract:

High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

US Patent:

20060256876, Nov 16, 2006

Filed:

May 15, 2006

Appl. No.:

11/383317

Inventors:

Andre Szczepanek - Hartwell, GB
Martin Li - Missouri City TX, US
Steven Marshall - Houston TX, US
Travis Scheckel - Allen TX, US

International Classification:

H04B 14/06

US Classification:

375246000

Abstract:

This invention enables many interrupt source bits spread among multiple interrupt registers. An interrupt status decode register reduces the number of read cycles required to decode the interrupt source. Each unique interrupt source has a predefined and fixed logical mapping to each bit of the decode register. The logical mapping is flexible per application. The decode register bit is set if the interrupt source is asserted and the interrupt source is mapped to that particular physical interrupt. Since each physical interrupt has an associated decode register, the ability to orthogonally arrange the sources and reduce the number of register reads is even greater.

US Patent:

20060256877, Nov 16, 2006

Filed:

May 15, 2006

Appl. No.:

11/383321

Inventors:

Andre Szczepanek - Hartwell, GB
Martin Li - Missouri City TX, US
Steven Marshall - Houston TX, US
Travis Scheckel - Allen TX, US

International Classification:

H04B 14/06

US Classification:

375246000

Abstract:

The Rapid I/O Messaging Logical Layer relies on the receiving device to map the incoming messages into specific memory locations. This uses software programmable mapping registers. The settings are compared to the header fields of the incoming Rapid I/O messages to determine if there is a match, in which case, the packet is mapped to a queue. Accessibility to a queue through the mapping register can be limited to discrete MAILBOX/LETTER combinations, or multiple combinations based on the masking bits. Long messages may be processed through a hardware lookup table implemented to break up transactions into Rapid I/O compliant packets.

US Patent:

20060256878, Nov 16, 2006

Filed:

May 15, 2006

Appl. No.:

11/383322

Inventors:

Andre Szczepanek - Hartwell, GB
Martin Li - Missouri City TX, US
Steven Marshall - Houston TX, US
Travis Scheckel - Allen TX, US

International Classification:

H04B 14/06

US Classification:

375246000

Abstract:

A packet transmission system based on a simple linear linked list of packet descriptors is difficult to implement with modern switch based system because transmission acknowledgments may occur out of order in relation to packet transmission. The problem lies in how packet completion is indicated to the CPU to enable for efficient packet processing. A scoreboard system is scalable to support multiple single-segment messages and multiple multi-segment messages for hundreds of packets. When a message/segment has been sent out, the context information for the packet is remembered and its key is indexed into a CAM. When segment/message response comes back, a simple hardware lookup is performed, and the associated context information is retrieved.

US Patent:

20060268714, Nov 30, 2006

Filed:

May 15, 2006

Appl. No.:

11/383316

Inventors:

Andre Szczepanek - Hartwell, GB
Martin Li - Missouri City TX, US
Steven Marshall - Houston TX, US
Travis Scheckel - Allen TX, US

International Classification:

H04J 1/16

US Classification:

370235000

Abstract:

The management of flows can be simplified by only keeping unique flow information for locally important flows, and aggregating all other flows together. A flow control table of 16 entries, 15 unique and 1 aggregate is usually sufficient, particularly in systems where the traffic flows are relatively static. This greatly reduces the required logic for Xoff/Xon counters and timeout monitors Rather than every packet source checking each packet it sends, the flows needed by each unit are registered in the flow table and the table logic indicates to each unit whether it has any blocked flows.

US Patent:

20100172355, Jul 8, 2010

Filed:

Mar 18, 2010

Appl. No.:

12/726727

Inventors:

Andre Szczepanek - Northampton, GB
Martin Yu Li - Missouri City TX, US
Steven P. Marshall - Houston TX, US
Travis M. Scheckel - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04L 12/56

US Classification:

370392, 370412

Abstract:

High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

US Patent:

50329863, Jul 16, 1991

Filed:

Sep 22, 1989

Appl. No.:

7/411180

Inventors:

Bimal Pathak - Stafford TX
Steven P. Marshall - Missouri City TX
James F. Potts - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1206

US Classification:

364200

Abstract:

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/subtractor in the auxiliary arithmetic logic units either adds or substracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register.

US Patent:

49087487, Mar 13, 1990

Filed:

Jul 28, 1987

Appl. No.:

7/078350

Inventors:

Bimal Pathak - Stafford TX
Steven P. Marshall - Missouri City TX
James F. Potts - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 500

US Classification:

364200

Abstract:

A microcomputer is disclosed which has an architecture designed for the efficient performance of digital signal processing applications. The microcomputer contains a primary arithmetic logic unit for performing data operations, and a pair of auxiliary arithmetic logic units for calculating indirect memory address values. A memory bus within the microcomputer has data lines therein, and two sets of address lines; each of the auxiliary arithmetic logic units is connected to one of the sets of address lines. The auxiliary arithmetic logic units are capable of performing circular addressing calculations, by calculating the next memory address from the prior memory address and an index value, and by comparing the next memory address to the limits of the memory block within the circular addressing scheme. If the calculated memory address is outside of the block limits, an adder/substractor in the auxiliary arithmetic logic units either adds or subtracts the block size to or from the calculated memory address, so that the result is an address at the other end of the block. The result of the calculation, whether or not modified, is stored in a memory address register.