Steven Allen Mcmahan

US Patent:

7007211, Feb 28, 2006

Filed:

Oct 4, 2002

Appl. No.:

10/264551

Inventors:

Christopher E. White - Plano TX, US
Steven C. McMahan - Richardson TX, US
John K. Eitrheim - Plano TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G11C 29/00

US Classification:

714718, 714733, 714 30

Abstract:

Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

US Patent:

7490276, Feb 10, 2009

Filed:

Oct 20, 2005

Appl. No.:

11/255383

Inventors:

Christopher E. White - Plano TX, US
Steven C. McMahan - Richardson TX, US
John K. Eitrheim - Plano TX, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01C 29/00
G01R 31/28

US Classification:

714718, 714733, 714734

Abstract:

Testing one or more memories of a device includes receiving one or more first repair records from one or more built-in self-testers of a device having one or more memories. A built-in self-tester is associated with a memory, and a first repair record describes a first repair at a memory. A first repair signature corresponding to the first repairs at the memories is generated from the first repair records, and then is recorded. One or more second repair records are received from the built-in self-testers, where a second repair record describes a second repair at a memory. A second repair signature corresponding to the second repairs at the memories is generated from the second repair records. The second repair signature is compared with the first repair signature. The device is evaluated in response to the comparison.

US Patent:

58595414, Jan 12, 1999

Filed:

Sep 15, 1993

Appl. No.:

8/122193

Inventors:

Steven Craig McMahan - Garland TX
Kenneth Charles Scheuer - Austin TX
William Burl Ledbetter - Austin TX
Michael Gordon Gallup - Austin TX
James George Gay - Pflugerville TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 1716
H03K 190175

US Classification:

326 30

Abstract:

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.

US Patent:

56447418, Jul 1, 1997

Filed:

Oct 18, 1993

Appl. No.:

8/138855

Inventors:

Mark W. Bluhm - Plano TX
Mark W. Hervin - Dallas TX
Steven C. McMahan - Richardson TX
Raul A. Garibay - Richardson TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

G06F 922

US Classification:

395376

Abstract:

A processor includes storage circuitry for storing an instruction and memory circuitry addressable by a microaddress for outputting a microinstruction in response to the microaddress. The processor further includes sequencing circuitry coupled to provide the microaddress to the memory circuitry. Finally, the processor includes decode circuitry coupled to the storage circuitry for detecting whether the instruction stored in the storage circuitry comprises a single clock instruction before the memory circuit outputs the microinstruction, and for indicating to the sequencing circuitry in response to detecting whether the instruction stored in the storage circuitry comprises a single clock instruction.

US Patent:

58359672, Nov 10, 1998

Filed:

Feb 27, 1996

Appl. No.:

8/607673

Inventors:

Steven C. McMahan - Richardson TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

G06F 938

US Classification:

711213

Abstract:

A prefetch unit is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. Normally, the prefetch unit performs split prefetching by generating low and high prefetch addresses in a single clock, with the high prefetch address being generated from the low prefetch address by incrementation. In cases where the low prefetch address is supplied to the prefetch unit too late in a clock period to generate the high prefetch address, such as where a branch instruction is not detected by a branch processing unit so that the target instruction address (i. e. , the low prefetch address) is supplied by an address calculation stage, the prefetch unit generates a prefetch request consisting of only the low prefetch address. In an exemplary embodiment each prefetch request is for an 8 byte block of instruction bytes, such that the high prefetch address is generated by adding an 8-bit value to the low prefetch address, and, for low prefetch addresses supplied late, the prefetch unit detects whether the low prefetch address has a �0! in bit position 3, and if so, generates the high prefetch address by toggling the bit position n to a �1! (because the no carry ripple will affect the higher order bits).

US Patent:

57322430, Mar 24, 1998

Filed:

Feb 28, 1996

Appl. No.:

8/607675

Inventors:

Steven C. McMahan - Richardson TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

G06F 1200

US Classification:

395464

Abstract:

A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a target cache organized in banks to support split prefetching. Prefetch requests (addressing a prefetch block of 16 bytes) are separated into low and high block addresses (addressing split blocks of 8 bytes). The low and high block addresses differ in bit position �3! designated a bank select bit, where the low block address of an associated prefetch request may be designated by a �1 or 0! such that a split block associated with a low block address may be allocated into either bank of the target cache (i. e. , the low block of a prefetch request can start on an 8 byte alignment rather than the 16 byte alignment). For each prefetch request that includes both low and high block addresses, respective banks of the target cache are successively accessed based on the state of the bank select bit, such that the low block address is used to access one bank and the high block address is used to access the other bank.

US Patent:

57713650, Jun 23, 1998

Filed:

Mar 1, 1995

Appl. No.:

8/396857

Inventors:

Steven C. McMahan - Richardson TX
Mark W. Bluhm - Plano TX

Assignee:

Cyrix Corporation - Richardson TX

International Classification:

G06F 1202

US Classification:

395381

Abstract:

A microarchitecture in a complex instruction computer system is disclosed employing a sparse microROM array and concatenation address circuitry for forming microaddress entry points, avoiding the need for a programmable logic array to translate instruction opcodes and avoiding duplicative entry points, thus minimizing the microROM array size.

US Patent:

52948455, Mar 15, 1994

Filed:

Aug 17, 1992

Appl. No.:

7/931187

Inventors:

Steven C. McMahan - Richardson TX
Kenneth C. Scheuer - Austin TX
William B. Ledbetter - Austin TX
Michael G. Gallup - Austin TX
James G. Gay - Pflugerville TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03K 19003

US Classification:

307443

Abstract:

A data processor has at least one output terminal which a user of the data processor can vary the output impedance thereof depending upon the application environment of the data processor. A first output buffer of an output buffer stage has a predetermined output impedance and is coupled between an input of the stage and the output terminal. The first output buffer provides a first output terminal impedance. A second output buffer having a lower output impedance than the first output buffer may be selectively coupled in parallel to the first output buffer to reduce the output impedance of the output terminal. The coupling of the output buffers is controlled by a user of the data processor who provides a control input for selecting one of a plurality of predetermined output terminal impedance values.