Steven L Merchant

US Patent:

6700160, Mar 2, 2004

Filed:

Oct 17, 2000

Appl. No.:

09/690263

Inventors:

Steven L. Merchant - Milford NH

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2976

US Classification:

257338, 257335, 257341, 257345

Abstract:

An improved DMOS power transistor ( ) with a single p-body implant ( ) and including an n-type channel compensating implant (NCCI) ( ). The improved DMOS power transistor ( ) provides a more favorable trade-off between threshold voltage (V ) and on-state resistance, while increasing the safe operating area (SOA). The NCCI ( ) also improves the off-state breakdown voltage, and allows a larger fraction of the gate bias voltage to be supported on the thin gate oxide ( ). The present invention can be fabricated using self-aligned fabrication techniques so that the channel length ( ) is insensitive to lithography equipment.

US Patent:

6797547, Sep 28, 2004

Filed:

Oct 3, 2003

Appl. No.:

10/679220

Inventors:

Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2100

US Classification:

438149, 438479, 438517, 438310, 438311, 438412, 438282, 257347, 257349, 257507

Abstract:

A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

US Patent:

6800917, Oct 5, 2004

Filed:

Dec 17, 2002

Appl. No.:

10/321423

Inventors:

Sheldon D. Haynie - Amherst NH
Steven L. Merchant - Bedford NH
Sameer P. Pendharkar - Richardson TX
Vladimir Bolkhovsky - Framingham MA

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2176

US Classification:

257506, 257524, 257E21553, 257E21564

Abstract:

A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post. The process can be used with conventional bulk silicon wafers and processes, and the blade devices can be integrated with conventional planar devices formed on other areas of the wafer.

US Patent:

6815276, Nov 9, 2004

Filed:

Oct 3, 2002

Appl. No.:

10/264038

Inventors:

Philip L. Hower - Concord MA
John Lin - Chelmsford MA
Sameer P. Pendharkar - Richardson TX
Steven L. Merchant - Bedford NH

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21336

US Classification:

438197, 438294

Abstract:

Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

US Patent:

7187034, Mar 6, 2007

Filed:

Jul 9, 2004

Appl. No.:

10/888776

Inventors:

Philip L. Hower - Concord MA, US
John Lin - Chelmsford MA, US
Sameer P. Pendharkar - Richardson TX, US
Steven L. Merchant - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/78

US Classification:

257341, 257401, 257E2912, 257E29256

Abstract:

Segmented power transistors and fabrication methods are disclosed in which transistor segments are spaced from one another to facilitate thermal diffusion, and in which other electrical devices can be formed in the spaces between transistor segments.

US Patent:

7417270, Aug 26, 2008

Filed:

Jun 23, 2004

Appl. No.:

10/874479

Inventors:

Philip L. Hower - Concord MA, US
David A. Walch - Bedford NH, US
John Lin - Chelmsford MA, US
Steven L. Merchant - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/80

US Classification:

257270, 257269, 257285, 257286, 257E27012

Abstract:

A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

US Patent:

7605412, Oct 20, 2009

Filed:

Sep 22, 2006

Appl. No.:

11/534395

Inventors:

Philip L. Hower - Concord MA, US
David A. Walch - Bedford NH, US
John Lin - Chelmsford MA, US
Steven L. Merchant - Bedford NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 31/112

US Classification:

257270, 257285, 257E2163, 438186

Abstract:

A Junction Field Effect Transistor (JFET) can be fabricated with a well region that include a channel region having an average dopant concentration substantially less the average doping concentration of the remaining portions of the well region. The lower average doping concentration of channel region compared to the remaining portions of the well region reduces the pinch-off voltage of the JFET.

US Patent:

7736961, Jun 15, 2010

Filed:

Jun 28, 2005

Appl. No.:

11/168047

Inventors:

Steven L. Merchant - Bedford NH, US
Philip L. Hower - Concord MA, US
Scott Paiva - Nashua NH, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/337

US Classification:

438186, 257E27148, 257E29265, 257E21403, 257E21421

Abstract:

A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.