Steven R O'Brien

US Patent:

50634941, Nov 5, 1991

Filed:

Apr 12, 1989

Appl. No.:

7/336980

Inventors:

Dennis J. Davidowski - Warminster PA
Michael J. Saunders - Norristown PA
Steven M. O'Brien - Norristown PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 900
G06F 300
G06F 1300

US Classification:

395800

Abstract:

The present invention provides a novel programmable data communications controller employed to accept data from a host computing system and for transmitting the data to a terminal designated by the host computer system. The data computer communications controller is further provided with protocols, parameters and poll tables stored in a dedicated memory of the data communications controller which enables the controller to receive data and address information from a main memory of a host computer and to reformat and pre-package the information in a protocol format block acceptable by a terminal coupled to the data communications controller. Different protocols, parameters and polls are provided in the data communications controller in the form of preprogrammed information which enables different terminals employing different protocols and protocol formats to be coupled directly to a data link interface bus without hardware modifications. Different protocols are loaded into the main memory of the main computer system and down loaded into the bit map memory of the data communications controller upon initialization of the system.

US Patent:

44371667, Mar 13, 1984

Filed:

Dec 23, 1980

Appl. No.:

6/219768

Inventors:

Steven M. O'Brien - Norristown PA

Assignee:

Sperry Corporation - New York NY

International Classification:

G06F 700
G06F 304

US Classification:

364900

Abstract:

In a high speed data processing system, there is provided a circuit for shifting either right or left as data is transmitted to or from the main storage unit. Apparatus for high speed parallel byte shifting is connected to the data bus which connects the main storage unit to the system and comprises logic which selects predetermined byte lines. Information from the individually selected byte lines is temporarily stored in parallel buffer registers and subsequently returned to a different byte line to provide byte shifting without the requirement of shift registers or complex logic.

US Patent:

43487424, Sep 7, 1982

Filed:

Jan 23, 1981

Appl. No.:

6/227859

Inventors:

Steven M. O'Brien - Norristown PA

Assignee:

Sperry Corporation - New York NY

International Classification:

G06F 1110

US Classification:

364900

Abstract:

Apparatus for checking the correct operation of a parallel byte shifter of the type having a plurality of input ports connected to individual byte lines of a data bus. When predetermined byte lines to the byte shifters are selected, control means are provided to activate a set of shift select means connected to error checking circuits. The error checking circuits comprise logic gating means for checking the proper selection of byte lines and for storing a signal indicative of an error or absence of an input error in the error storage means. When the data byte is being transferred out or read out of the byte shifter, the error storage means is read out to determine the presence or absence of an output error from the error storage means.

US Patent:

51796910, Jan 12, 1993

Filed:

Apr 12, 1989

Appl. No.:

7/336971

Inventors:

Steven M. O'Brien - Norristown PA
Arthur J. Nilson - Norristown PA
Jayant S. Pandya - Center Square PA
Michael J. Saunders - Norristown PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 9455
G06F 930
G06F 300

US Classification:

395500

Abstract:

An apparatus for enhancing the operation of a M byte instruction word CPU when operating user programs on an N byte instruction word CPU. The M-Byte instruction word CPU is provided with an N-Byte instruction register and a main memory for supplying N-Byte instruction words or M-Byte instruction words to said N-Byte instruction register. An operational code multiplexer and an parameter code multiplexer are connectable to selective outputs of said instruction register so that any one of the M-Bytes may be selected as an operational code and any one of the remaining M-Bytes may be selected as parameter code bytes, and selection means including sequencer means are provided for operating the operational code multiplexer and the parameter code multiplexer in an M-Byte instruction word CPU mode of operation or as an N-Byte instruction word CPU mode of operation.

US Patent:

52789730, Jan 11, 1994

Filed:

Jun 27, 1991

Appl. No.:

7/722722

Inventors:

Steven M. O'Brien - Norristown PA
Michael J. Saunders - Norristown PA
Arthur J. Nilson - Norristown PA

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 922

US Classification:

395500

Abstract:

A mainframe computing system is adapted to be loaded with one of a plurality of different operating systems and different associated microcode to provide a computing system which is capable of running user programs adapted to be executed by the loaded operated system comprises a main memory for receiving the desired operating system coupled to a system bus. An instruction processor and an input/output control processor are coupled to the system bus and are provided with an instruction register for presenting user program instructions to the processors. The processor means have associated therewith microcode storage memory which receive and store a set of microcode instructions to be performed by the processors according to the program instruction stored in the instruction register. The stored microcode comprises primary microcode instructions to carry out each of the instructions in the instruction register means. No compiling or emulation is necessary to provide a software configurable computing system adapted to run user programs according to one of a plurality of operating systems loadable in the main memory.

US Patent:

43864015, May 31, 1983

Filed:

Jul 28, 1980

Appl. No.:

6/172619

Inventors:

Steven M. O'Brien - Norristown PA

Assignee:

Sperry Corporation - New York NY

International Classification:

G06F 104
G06F 1300

US Classification:

364200

Abstract:

The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.

US Patent:

20140122778, May 1, 2014

Filed:

Mar 29, 2013

Appl. No.:

13/853110

Inventors:

Unisys Corporation - , US
Steven Michael O'Brien - Malvern PA, US

Assignee:

Unisys Corporation - Blue Bell PA

International Classification:

G06F 3/06

US Classification:

711103, 711114

Abstract:

Systems and methods are disclosed herein to a data storage tiering system comprising at least one storage array; at least one solid state storage unit; and a storage controller in communication with the at least one storage array and the at least one solid state storage unit and configured to combine the at least one storage array and the at least one solid state storage unit into one business tier data container using a virtualization layer and present the business tier data container on a storage area network as one storage array to a server, wherein the storage controller creates a business data tier by combining a partition of the solid state storage unit with the at least one storage array.