Steven Wesley Reid

US Patent:

6621241, Sep 16, 2003

Filed:

Dec 20, 2001

Appl. No.:

10/028501

Inventors:

Steven L. Reid - Torrance CA
John R. Keller - Santa Barbara CA
Joseph K. Bond - Newbury Park CA

Assignee:

DAC International, Inc. - Carpinteria CA

International Classification:

H02K 3300

US Classification:

318114, 318460, 318119, 1731621, 81463

Abstract:

A system and method for reducing reaction forces induced in a machine frame by an oscillating tool employs a counterforce assembly which is driven to move along linear slides mounted to the machine frame. The counterforce assembly is driven with a drive signal derived from two signals: a first signal which is proportional to the acceleration of the tool, and a second signal which is directly proportional to the velocity of the oscillating tool. By properly-adjusting the acceleration and velocity components of the drive signal, the magnitude of the reaction forces induced in the machine frame by the oscillating tool can be substantially reduced. The counterforce assembly preferably includes a centering means which prevents it from moving to either end of the slide. An accelerometer is preferably mounted to the machine frame to sense its vibration, with the accelerometer output used to adjust the counterforce assemblys drive electronics to reduce vibration to a minimum.

US Patent:

41410688, Feb 20, 1979

Filed:

Mar 24, 1977

Appl. No.:

5/780875

Inventors:

George E. Mager - Manhattan Beach CA
Frank M. Nelson - Sherman Oaks CA
Steven L. Reid - Redondo Beach CA
Philip Richardson - Pacific Palisades CA
Vernon E. Rochat - Palos Verdes CA
Donald S. Post - Fairport NY

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06F 1300

US Classification:

364200

Abstract:

An auxiliary ROM memory system which is hierarchied for providing for the contingency of additional read-only memory control program storage requirements in excess or in lieu of the predetermined ROM memory provided on-board a microprocessor based central processing unit module, and a read-only memory altering capability utilizing programmable read-only memory to expedite the implementation/installation of changes to the ROM bit patterns. The alterable PROM storage comprises bulk PROM memory including a first PROM set that is mutually exclusive as to existing on-board ROM memory for addressably branching to code extensions and/or in-line code insertions, and/or a second PROM set that is mutually inclusive as to existent on-board and contingent ROM memory for decodably addressing large-scale code overlays thereto. In addition, the alterable PROM storage comprises patch PROM for addressing, through multi-leveled decoding, small-scale code overlays to the on-board and contingent ROM memory for single in-line bit pattern alterations. Conflicting memory requests involving addresses recognized by more than one of the supra memory categories, when enabled, are presented to a predetermined hierarchy of memory precedences for resolution thereof.