Steven P Rose

US Patent:

43204503, Mar 16, 1982

Filed:

Oct 30, 1979

Appl. No.:

6/089493

Inventors:

Steven A. Rose - Glendale AZ
Edward H. Forrester - Phoenix AZ

Assignee:

Honeywell Inc. - Minneapolis MN

International Classification:

G06F 1516
G06F 1130

US Classification:

364200

Abstract:

In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input signals to the interface structure. The interface structure then translates those signals into an attention flag signal and signals identifying the source or nature of the emergency. The firmware engine then responds to those signals and effects the necessary measures to protect the data relative to the affected CPU.

US Patent:

47648961, Aug 16, 1988

Filed:

Jul 1, 1985

Appl. No.:

6/750797

Inventors:

Ronald J. Freimark - Scottsdale AZ
Steven A. Rose - Mesa AZ

Assignee:

Honeywell Inc. - Phoenix AZ

International Classification:

G06F 900

US Classification:

364900

Abstract:

An apparatus for controlling data movement between a peripheral and a data processing system, comprises a memory for storing data, wherein the memory comprises a plurality of memory modules. Each memory module corresponds to an assigned area of a first memory map, the first memory map being duplicated into a plurality of mirrored memory maps. Each mirrored memory map corresponds to a predefined operation, a composite of the first memory map and the plurality of mirrored memory maps forming a total memory space. Each memory location within the total memory space is defined by a unique memory space address. A processor performs a pseudo operation in response to a first control signal from the peripheral indicating data is available for being moved. A logic circuit generates at least one control signal in response to the pseudo operation such that a predetermined data movement operation occurs.