Steven E Sharp

US Patent:

7739629, Jun 15, 2010

Filed:

Oct 30, 2006

Appl. No.:

11/590657

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2, 716 7, 703 14

Abstract:

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

US Patent:

8516422, Aug 20, 2013

Filed:

Jun 14, 2010

Appl. No.:

12/815239

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghao Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716109, 716111, 716120, 716123, 716133, 716127, 716136, 703 16

Abstract:

A method for implementing a single file format for power-related information for an IC comprising: providing a circuit design in at least one design file in a non-transitory computer readable storage device; providing power-related design information in a file in the computer readable storage device that is separate from the at least one design file and that specifies multiple power domains within the circuit design, each power domain including one or more design object instances from within the circuit design and that specifies multiple power modes each power mode corresponding to a different combination of on/off states of the multiple specified power domains and that specifies isolation behavior relative to respective power domains; and using a computer to add power control circuitry to the circuit design that implements the power domains and power modes and isolation behavior specified in the power specification information.

US Patent:

RE44479, Sep 3, 2013

Filed:

Jun 12, 2012

Appl. No.:

13/494363

Inventors:

Qi Wang - San Jose CA, US
Ankur Gupta - Mountain View CA, US
Pinhong Chen - Saratoga CA, US
Christina Chu - San Jose CA, US
Manish Pandey - San Jose CA, US
Huan-Chih Tsai - Saratoga CA, US
Sandeep Bhatia - San Jose CA, US
Yonghoa Chen - Groton MA, US
Steven Sharp - Lowell MA, US
Vivek Chickermane - Ithaca NY, US
Patrick Gallagher - Appalachian NY, US
Mitchell W. Hines - San Jose CA, US

Assignee:

Cadence Design Systems, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716105, 716102, 716103, 703 14

Abstract:

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.