Steven J Smolski

US Patent:

7386759, Jun 10, 2008

Filed:

Jan 27, 2005

Appl. No.:

11/044553

Inventors:

Kevin Gene Kehne - Austin TX, US
Claudia Andrea Salzberg - Austin TX, US
Steven Joseph Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 6, 714 11, 714 12

Abstract:

A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be referred to as data acquisition. The data from one device and the data from the other device may be compared to each other. This may be referred to as data validation. When data is exchanged during data acquisition, it is also stored in appropriate locations in a pool of buffers in memory. During the data acquisition, checks are made to determine if the system is entering an idle cycle. If so, the data validation test is performed by using the data in the pool of buffers in memory.

US Patent:

7392441, Jun 24, 2008

Filed:

Jan 10, 2005

Appl. No.:

11/032179

Inventors:

Kevin Gene Kehne - Austin TX, US
Claudia Andrea Salzberg - Austin TX, US
Steven Joseph Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714709, 714 30, 714 31

Abstract:

A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

US Patent:

7430487, Sep 30, 2008

Filed:

Sep 6, 2006

Appl. No.:

11/470282

Inventors:

Michael Criscolo - Cedar Park TX, US
Christopher J. Kuruts - Round Rock TX, US
James P. Kuruts - Round Rock TX, US
Steven J. Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G11C 29/00
G06F 19/00

US Classification:

702117, 702186, 714718

Abstract:

A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.

US Patent:

7624312, Nov 24, 2009

Filed:

May 31, 2008

Appl. No.:

12/131068

Inventors:

Kevin Gene Kehne - Austin TX, US
Claudia Andrea Salzberg - Austin TX, US
Steven Joseph Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03M 13/00

US Classification:

714709, 714 6, 714 30, 714 31

Abstract:

A system, apparatus, computer program product and method of performing operational validation on a system are provided. The system may include a CPU with a cache, a communications network, and a plurality of devices exchanging data during a test. When the test is ready to be performed, the CPU may set up a pool of buffers in the cache. The pool of buffers may generally have a set of locations corresponding to locations in an actual destination buffer and a set of locations corresponding to locations in an actual source buffer. During the performance of the test, data is exchanged over the communications network to and from the source and destination buffers. Snooping logic in the cache may snoop data on the communications network. The data snooped may be entered in appropriate locations in the pool of buffers. This allows the CPU to perform operational validation by using cached data instead of data that is in the actual source and destination buffers.

US Patent:

7689865, Mar 30, 2010

Filed:

Sep 6, 2006

Appl. No.:

11/470478

Inventors:

Heinz Baier - Sindelfingen, DE
Christopher R. Conley - Pflugerville TX, US
Brian Flachs - Georgetown TX, US
Michael T. Saunders - Round Rock TX, US
Steven J. Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 30, 714 28

Abstract:

A method, device, system, and computer program product for enabling advanced control of debugging processes on a JTAG (Joint Test Action Group) IEEE 1149. 1 capable device (or system under test (SUT)). Middlesoft Commander is provided within a JTAG-enabled (or JTAG) POD, which is connected to both a host system executing debugging software and the SUT. The communication between the POD and the SUT is enabled with a pair of JTAG interfaces bridging the connection between the POD and the SUT. Middlesoft Commander comprises code that enables Middlesoft Commander to convert high level commands (debug packets) received from (or generated by) the host system into JTAG commands. These JTAG commands are forwarded to the SUT. Middlesoft Commander further comprises code that enables Middlesoft Commander to convert the JTAG data received from the SUT into commands recognizable by the host system.

US Patent:

7721145, May 18, 2010

Filed:

May 27, 2008

Appl. No.:

12/127758

Inventors:

Kevin Gene Kehne - Austin TX, US
Claudia Andrea Salzberg - Austin TX, US
Steven Joseph Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 6, 714819, 710 65

Abstract:

A system, apparatus, computer program product and method of performing functional validation testing in a system are provided. Generally, functional validation testing includes data acquisition and data validation testing. During the functional validation testing two devices may be exchanging data. The exchange of data by the two devices may be referred to as data acquisition. The data from one device and the data from the other device may be compared to each other. This may be referred to as data validation. When data is exchanged during data acquisition, it is also stored in appropriate locations in a pool of buffers in memory. During the data acquisition, checks are made to determine if the system is entering an idle cycle. If so, the data validation test is performed by using the data in the pool of buffers in memory.

US Patent:

7818619, Oct 19, 2010

Filed:

Aug 30, 2007

Appl. No.:

11/847333

Inventors:

Steven Joseph Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/00

US Classification:

714 25, 714 27, 714 31

Abstract:

A test system includes a debugging system and a system under test (SUT). The debugging system includes a debugging processor that couples to an SUT processor in the SUT via a memory mapping interface bus therebetween. In one embodiment, the debugging processor operates as a master to conduct test operations on the SUT via the memory mapping interface bus. The debugging processor and the SUT processor operate together in a cluster mode to provide non-invasive debugging of the (SUT) while the SUT executes application software in a real time environment.

US Patent:

8165847, Apr 24, 2012

Filed:

Aug 6, 2008

Appl. No.:

12/187199

Inventors:

Michael Criscolo - Cedar Park TX, US
Christopher J. Kuruts - Round Rock TX, US
James P. Kuruts - Round Rock TX, US
Steven J. Smolski - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/30
G11C 29/00

US Classification:

702186, 714718, 714719

Abstract:

A method, system, and computer-usable medium for implementing a programmable DMA master with data checking utilizing a drone system controller. According to an embodiment of the present invention, a drone processor generates a collection of random data and stores a first and second copy of the collection of random data in a first and second memory location in a drone memory. The drone processor writes a third copy of the collection of random data in a processor memory. When the drone processor retrieves the third copy from the processor memory, the drone processor writes the third copy in the second memory location in the drone memory. When the drone processor compares the first copy with the third copy, the results of the compare is written in a status location within the drone processor.