Steven J Sullivan

US Patent:

6581140, Jun 17, 2003

Filed:

Jul 3, 2000

Appl. No.:

09/609749

Inventors:

Steven C. Sullivan - Austin TX
Michael D. Snyder - Austin TX
Magnus K. Bruce - Cedar Park TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1200

US Classification:

711128, 711204, 711213

Abstract:

A system provides a method and apparatus for accessing information in a cache in a data processing system. The system optimizes a speed-critical path within the cache system by using a prediction scheme. The prediction scheme subdivides the address range of address bits and compares the portions separately. A comparison of a critical portion of the address, along with a prediction bit, are used to generate a prediction.

US Patent:

6608789, Aug 19, 2003

Filed:

Dec 21, 2001

Appl. No.:

10/027547

Inventors:

Steven C. Sullivan - Austin TX
Perry H. Pelley - Austin TX
George P. Hoekstra - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700

US Classification:

365205, 365203, 365207, 327 51, 327 52, 327 55

Abstract:

A sense amplifier ( ) uses a body shorting device ( ) to selectively electrically short circuit the bodies of two transistors ( ) that function as a differential sensing pair. Equalization of charge injected into the bodies functions to minimize offset voltage between the two bodies. The body shorting device selectively shorts the bodies in response to a body control signal after a sense operation and after asserting a precharging signal to initiate precharging of the sense amplifiers outputs.

US Patent:

8432756, Apr 30, 2013

Filed:

Oct 18, 2011

Appl. No.:

13/275920

Inventors:

Steven C. Sullivan - Austin TX, US
William V. Miller - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

365195, 36523005, 36518914

Abstract:

A dual port memory includes a mechanism for preventing collisions. The memory includes dual port bit cells arranged in rows and columns and each bit cell stores a data bit. The memory also includes a wordline unit that may provide a respective write wordline signal and a respective read wordline signal to each row of bit cells. The wordline unit may also selectively inhibit the read wordline signal for a given row based upon address information that is indicative of whether a write operation will be performed to the given row.

US Patent:

8472267, Jun 25, 2013

Filed:

Jun 20, 2011

Appl. No.:

13/164382

Inventors:

Abhijeet R. Tanpure - Austin TX, US
Steven C. Sullivan - Austin TX, US
William V. Miller - Austin TX, US
Jason A. Frerich - Bastrop TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 7/00

US Classification:

36518915, 36518905, 365205

Abstract:

Sense amplifiers in a memory may be activated and deactivated. In one embodiment, a processor may include a memory. The memory may include a number of sense amplifiers. Based on a late arriving address bit of an address used to access data from the memory, a sense amplifier may be activated while another sense amplifier may be deactivated.

US Patent:

8570827, Oct 29, 2013

Filed:

Jun 20, 2011

Appl. No.:

13/164306

Inventors:

Steven C. Sullivan - Austin TX, US
Abhijeet R. Tanpure - Austin TX, US
William V. Miller - Austin TX, US
Ben D. Jarrett - Austin TX, US

Assignee:

Apple Inc. - Cupertino CA

International Classification:

G11C 8/08

US Classification:

36523006, 36523004, 36523003, 36523002, 36518905, 36518902, 365 491, 365229, 365227

Abstract:

Controllable arrays in a memory may be activated and deactivated independently. In one embodiment, a processor may include a memory. The memory may be a de-interleaved memory with independently selectable arrays. Based on an address bit of an address used to access data from the memory, a wordline and downstream components may be activated while another wordline and downstream components may be deactivated.

US Patent:

20130091329, Apr 11, 2013

Filed:

Oct 11, 2011

Appl. No.:

13/270653

Inventors:

Steven C. Sullivan - Austin TX, US

International Classification:

G06F 12/08
G11C 29/04
G11C 7/06

US Classification:

711118, 365207, 365200, 711E12017

Abstract:

A memory column redundancy mechanism includes a memory having a number of data output ports each configured to output one data bit of a data element. The memory also includes a number of memory columns each connected to a corresponding respective data port. Each memory column includes a plurality of bit cells that are coupled to a corresponding sense amplifier that may differentially output a respective data bit from the plurality of bit cells on an output signal and a complemented output signal. The memory further includes an output selection unit that may select as the output data bit for a given data output port, one of the output signal of the sense amplifier associated with the given data output port or the complemented output signal of the sense amplifier associated with an adjacent data output port dependent upon a respective shift signal for each memory column.

US Patent:

55306764, Jun 25, 1996

Filed:

Jan 27, 1995

Appl. No.:

8/379807

Inventors:

Steven C. Sullivan - Austin TX
Michael L. Brauer - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 700

US Classification:

365227

Abstract:

A clock signal (202) is received, wherein the rising edge of the clock signal (202) controls an operation of a memory cell (224) of a memory circuit (200). Address information (204) is received and predecoded prior to the rising edge of the clock signal (202) to produce a row select signal (210). A control signal (201), which is received prior to the rising edge of the clock signal, determines whether the operation is a read operation or a write operation. If the operation is a write operation, new data information (218) is received a data delay after the rising edge of the clock signal (202); the row select signal (210) is delayed such that the memory cell (224) is selected at least a data delay after the rising edge of the clock signal (202); and the new data information (218) is written to the memory cell (224).

US Patent:

61870382, Feb 13, 2001

Filed:

Apr 8, 1998

Appl. No.:

9/056956

Inventors:

Steven G. Sullivan - Austin TX
Donald E. Chickering - Framingham MA
John P. Ranieri - Austin TX

Assignee:

Sulzer Carbomedics Inc. - Austin TX

International Classification:

A61F 200

US Classification:

623 143

Abstract:

A composite graft for a fluid-carrying vessel in a living body, comprising: an inner vessel comprising a biologic collagenic material that has been stabilized, an outer member surrounding at least a segment of the inner vessel and defining an annulus between the inner vessel and the sleeve, the outer member comprising a polymeric fabric, and a bioactive compound in said annulus, said bioactive compound being carried on a time-release vehicle. The bioactive compound is preferably an occlusion-preventing agent. Alternatively, the sleeve includes the bioactive compound, either on its inner surface or integrally as part of its fibers.