Steven R Testa

US Patent:

7423870, Sep 9, 2008

Filed:

Nov 18, 2005

Appl. No.:

11/282269

Inventors:

James L. Carlisi - Raleigh NC, US
Keith D. Richeson - Cary NC, US
Steven R. Testa - Durham NC, US
John K. Whetzel - Holly Springs NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/16

US Classification:

361686, 713170, 280 4726, 710303

Abstract:

A blade server assembly is disclosed that includes a blade server chassis, a blade server, and a support assembly connected with the blade server chassis and with the blade server so as to support the blade server substantially outside the blade server chassis. A method is also disclosed for maintaining a blade server installed in a blade server chassis that includes supporting the blade server substantially outside the blade server chassis through a support assembly connected with the blade server chassis and with the blade server.

US Patent:

7711930, May 4, 2010

Filed:

Oct 8, 2007

Appl. No.:

11/868557

Inventors:

James N. Dieffenderfer - Apex NC, US
Richard W. Doing - Raleigh NC, US
Brian M. Stempel - Raleigh NC, US
Steven R. Testa - Durham NC, US
Kenichi Tsuchiya - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712219, 712235

Abstract:

A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

US Patent:

7940521, May 10, 2011

Filed:

Jun 27, 2008

Appl. No.:

12/147713

Inventors:

James L. Carlisi - Raleigh NC, US
Keith D. Richeson - Cary NC, US
Steven R. Testa - Durham NC, US
John K. Whetzel - Holly Springs NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/16

US Classification:

36167941, 280 4726, 710303, 713170

Abstract:

A blade server assembly is disclosed that includes a blade server chassis, a blade server, and a support assembly connected with the blade server chassis and with the blade server so as to support the blade server substantially outside the blade server chassis. A method is also disclosed for maintaining a blade server installed in a blade server chassis that includes supporting the blade server substantially outside the blade server chassis through a support assembly connected with the blade server chassis and with the blade server.

US Patent:

8015565, Sep 6, 2011

Filed:

Nov 21, 2005

Appl. No.:

11/284257

Inventors:

Richard William Doing - Raleigh NC, US
John R. Patty - Cary NC, US
Steven Robert Testa - Durham NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/46

US Classification:

718102, 718104, 718100

Abstract:

A method, and apparatus are provided for preventing livelocks in processor selection of load requests in a multiprocessor (MP) system. On random occasions a selection mechanism is changed for first holding up all requests and then a random selection is made. Then a round robin selection mechanism is used for further requests. A livelock-preventing selection mechanism includes a pair of linear feedback shift registers (LFSRs), each LFSR for generating pseudo random values.

US Patent:

20050216703, Sep 29, 2005

Filed:

Mar 26, 2004

Appl. No.:

10/810235

Inventors:

James Dieffenderfer - Apex NC, US
Richard Doing - Raleigh NC, US
Brian Stempel - Raleigh NC, US
Steven Testa - Durham NC, US
Kenichi Tsuchiya - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F009/40

US Classification:

712207000

Abstract:

A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the processing stream due to an execution of a branch correction, or when an interrupt changes the sequence of an instruction stream. The latency is reduced when a decode stage for detecting branch prediction and a related instruction queue location have invalid data representing a bubble in the processing stream. Instructions for execution are inserted in parallel into the decode stage and instruction queue, thereby reducing by one cycle time the length of the pipeline stage.

US Patent:

20060155961, Jul 13, 2006

Filed:

Jan 6, 2005

Appl. No.:

11/030339

Inventors:

James Dieffenderfer - Apex NC, US
Richard Doing - Raleigh NC, US
Sanjay Patel - Cary NC, US
Steven Testa - Durham NC, US
Kenichi Tsuchiya - Cary NC, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - ARMONK NY

International Classification:

G06F 9/30

US Classification:

712204000

Abstract:

Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.