Steven Kalden Watkins

US Patent:

7778252, Aug 17, 2010

Filed:

May 18, 2006

Appl. No.:

11/436234

Inventors:

Steven K. Watkins - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H04L 12/28
H04L 7/00
H04J 3/06

US Classification:

37039562, 370509, 370518, 370520, 375355, 375356

Abstract:

Local Interconnect Network message budget calculation error is reduced by utilizing an eight bit time measurement of the sync byte in the message header. The method determines the header budget separately from the data budget, simplifying the required logic. The sync byte reference time is multiplied by the message data size to determine the data budget.

US Patent:

20160091561, Mar 31, 2016

Filed:

Sep 30, 2014

Appl. No.:

14/502406

Inventors:

- AUSTIN TX, US
JAMES B. EIFERT - AUSTIN TX, US
STEFANO PIETRI - AUSTIN TX, US
STEVEN K. WATKINS - AUSTIN TX, US

International Classification:

G01R 31/28

Abstract:

An integrated circuit includes a normal voltage detector configured to detect a normal voltage at which the integrated circuit being fully functional. A first voltage detector detects a first voltage that is less than the normal voltage. A second voltage detector detects a second voltage that is less than the first voltage. A reset module is coupled to a supply voltage, the normal voltage detector, the first voltage detector, and the second voltage detector. The reset module includes test logic to, when the supply voltage rises to the first voltage from the second voltage, perform a pass/fail test when the integrated circuit is in a pass/fail test mode, and perform a power up reset when the integrated circuit in not in the pass/fail test mode.

US Patent:

20150116030, Apr 30, 2015

Filed:

Oct 30, 2013

Appl. No.:

14/067320

Inventors:

ANIS M. JARRAR - Austin TX, US
Stefano Pietri - Lakeway TX, US
Steven K. Watkins - Austin TX, US

International Classification:

H03K 17/16

US Classification:

327536, 327537

Abstract:

A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.