Steven L Webber

US Patent:

39797260, Sep 7, 1976

Filed:

Apr 10, 1974

Appl. No.:

5/459504

Inventors:

Ronald Edwin Lange - Phoenix AZ
Riley H. Dobberstein - Scottsdale AZ
Steven Hugh Webber - Groton MA

Assignee:

Honeywell Information Systems, Inc. - Phoenix AZ

International Classification:

G06F 1300

US Classification:

3401725

Abstract:

In a data processing system that uses segmentation and paging to access data information such as in a virtual memory machine, the cache store need not be entirely cleared each time an I/O operation is performed or each time the data in the cache has a possibility of being incorrect. With segmentation and paging, only a portion of the cache store need be cleared when a new page is obtained from the virtual memory. The entire cache store is cleared only when a new segment is indicated by the instruction. The cache store is selectively cleared of the information from the page whose data information is no longer needed by addressing each level of an associative tag directory to the cache store. The columns of each level are compared to the page address and if a comparison is signaled that column of the addressed level is cleared by clearing the flag indicating the full status of the column in the addressed level. Each level of the tag directory is addressed.