Subhash Gupta

US Patent:

6515342, Feb 4, 2003

Filed:

Apr 25, 2000

Appl. No.:

09/557680

Inventors:

Subhash Gupta - San Jose CA
Bhanwar Singh - Morgan Hill CA
Carmen Morales - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2900

US Classification:

257506, 438790, 430317, 257347

Abstract:

A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

US Patent:

56584407, Aug 19, 1997

Filed:

Nov 6, 1995

Appl. No.:

8/553966

Inventors:

Michael K. Templeton - Mountain View CA
Subhash Gupta - San Jose CA

Assignee:

Advanced Micro Devices Incorporated - Sunnyvale CA

International Classification:

C23C 1434

US Classification:

20419237

Abstract:

A process called surface image transfer etching (SITE) is used to etch patterned photoresist so as to more completely transfer a well-defined pattern formed in the top surface (10a) of a material to the bulk of the material (12). The process uses no mask, but employs only a sputter etching process where the etching rates of surfaces not normal to the ion trajectories are greatly enhanced over the etching rates of surfaces normal to the ion trajectories.

US Patent:

56912382, Nov 25, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/478321

Inventors:

Steven Avanzino - Cupertino CA
Subhash Gupta - San Jose CA
Rich Klein - Mountain View CA
Scott D. Luning - Menlo Park CA
Ming-Ren Lin - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2144

US Classification:

437195

Abstract:

A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first used to etch completely through the layer to form conductive line openings. The openings are completely filled with a conductive material and planarized so that the surfaces of the conductive material and the insulating layer are coplanar. A via pattern is aligned perpendicular to the conductive lines and the conductive material is etched half way through the conductive lines in other than the areas covered by the via pattern. The openings thus created in the upper portion of the conductive lines are filled with insulating material to complete the dual damascene interconnection level with the conductive lines in the lower portion of the insulating layer and upwardly projecting vias in the upper portion of the layer. In addition, a triple damascene layer is formed by starting with an insulating layer about one-third thicker than normal and by combining the standard dual damascene method with the above described method.

US Patent:

58145605, Sep 29, 1998

Filed:

Nov 29, 1995

Appl. No.:

8/564752

Inventors:

Robin W. Cheung - Cupertino CA
Simon S. Chan - Saratoga CA
Subhash Gupta - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438648

Abstract:

A method is provided for forming metal interconnect structures which resists the formation of pile-ups caused by electromigration. Each metal interconnect structure includes an aluminum interconnect sandwiched between two refractory metal layers. The method of the present invention involves forming a layer of aluminum intermetallic alloy on the sidewalls of the aluminum interconnects. The layer of aluminum intermetallic alloy provides reinforcement for the sidewalls. The layer of aluminum intermetallic alloy comprises aluminum-refractory metal alloy. The aluminum-refractory metal alloy is formed by reacting the exposed aluminum on the sidewalls with refractory metal-containing precursor material. After the formation of the layer of aluminum intermetallic alloy the sidewalls of the aluminum interconnects, the formation of pile-ups will be suppressed. Thus, the lifetime of the aluminum interconnects is extended.

US Patent:

60665785, May 23, 2000

Filed:

Dec 1, 1997

Appl. No.:

8/980888

Inventors:

Subhash Gupta - San Jose CA
Bhanwar Singh - Morgan Hill CA
Carmen Morales - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03C 500

US Classification:

438790

Abstract:

A system and method for forming a plurality of structures in a low dielectric constant layer is disclosed. The low dielectric constant layer is disposed on a semiconductor. The method and system include exposing the low dielectric constant layer to an agent that improves adhesion of a photoresist, providing a layer of the photoresist on the low dielectric constant layer, patterning the photoresist, and etching the low dielectric constant layer to form the plurality of structures.

US Patent:

49620649, Oct 9, 1990

Filed:

May 12, 1988

Appl. No.:

7/193478

Inventors:

Jacob D. Haskell - Palo Alto CA
Craig S. Sander - Mountain View CA
Steven C. Avanzino - Cupertino CA
Subhash Gupta - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21465

US Classification:

437228

Abstract:

A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: deposition, over an integrated circuit structure having first portions at a height higher than the remainder of the integrated circuit structure, a conformal oxide layer; depositing a layer of a planarizing material such as polysilicon over the conformal oxide layer; polishing the structure a first time to expose the highest portions of the underlying conformal oxide layer; etching the structure a first time with an etchant system capable of removing the conformal oxide preferentially to the planarizing material; further polishing the structure a second time to remove planarizing material left from the first etching step; and then optionally etching the remainder of the structure to remove any remaining planarizing material and the remaining conformal oxide over the raised portions of the underlying integrated circuit structure to provide the desired highly planarized structure.

US Patent:

51982986, Mar 30, 1993

Filed:

Oct 24, 1989

Appl. No.:

7/426147

Inventors:

Jacob D. Haskell - Palo Alto CA
Subhash Gupta - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

B32B 3300

US Classification:

428336

Abstract:

An etch stop player (22) for permitting distinguishing between two similar layers (20, 24), such as two oxide layers, during etching is provided. The etch stop layer comprises a silicon-oxyhalide polymer, preferably a silicon-oxyfluoride polymer. Use of the polymer as an etch stop layer permits closer placement of metal conductor surfaces (12, 12') and contacts (14').

US Patent:

56147651, Mar 25, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/478319

Inventors:

Steven Avanzino - Cupertino CA
Subhash Gupta - San Jose CA
Rich Klein - Mountain View CA
Scott D. Luning - Menlo Park CA
Ming-Ren Lin - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2348
H01L 2352
H01L 2940

US Classification:

257774

Abstract:

An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive lines contains laterally enlarged areas where the via openings are to formed in the insulating material. After the conductive line openings with laterally enlarged areas are created, the openings are filled with a conformal material whose etch selectivity is substantially less than the etch selectivity of the insulating material to the enchant for etching the insulating material and whose etch selectivity is substantially greater than the insulating material to its enchant. The conformal material is anisotropically etched to form sidewalls in the enlarged area and remove the material between the sidewalls but leave material remaining in the parts of the conductive lines openings. The sidewalls serve as self aligned mask for etching via openings.