Subhash S Mahajan

US Patent:

7732306, Jun 8, 2010

Filed:

Jul 25, 2008

Appl. No.:

12/180370

Inventors:

Chantal Arena - Mesa AZ, US
Subhash Mahajan - Tempe AZ, US
Ranjan Datta - Tempe AZ, US

Assignee:

S.O.I.Tec Silicon on Insulator Technologies - Bernin

International Classification:

H01L 21/36
H01L 21/20
H01L 21/00
H01L 21/331
H01L 21/203

US Classification:

438481, 438 41, 438341, 257E2109, 257E21097, 257E21461

Abstract:

This invention provides methods for fabricating substantially continuous layers of group III nitride semiconductor materials having low defect densities. The methods include epitaxial growth of nucleation layers on a base substrate, thermally treatment of said nucleation layer and epitaxial growth of a discontinuous masking layer. The methods outlined promote defect reduction through masking, annihilation and coalescence, therefore producing semiconductor structures with low defect densities. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e. g. , combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e. g. , group II-VI and group III-V compound semiconductor materials.

US Patent:

8236593, Aug 7, 2012

Filed:

May 14, 2008

Appl. No.:

12/600120

Inventors:

Chantal Arena - Mesa AZ, US
Subhash Mahajan - Tempe AZ, US
Ilsu Han - Tempe AZ, US

Assignee:

Soitec - Bernin
Arizona Board of Regents for and on Behalf of Arizona State University - Scottsdale AZ

International Classification:

H01L 21/00

US Classification:

438 44, 438481, 257E21097, 257E21461, 257E21566

Abstract:

The invention provides methods which can be applied during the epitaxial growth of two or more layers of semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects present in one epitaxial layer are capped with a masking material. A following layer is then grown so it extends laterally above the caps according to the known phenomena of epitaxial lateral overgrowth. The methods of the invention can be repeated by capping surface defects in the following layer and then epitaxially growing a second following layer according to ELO. The invention also includes semiconductor structures fabricated by these methods.

US Patent:

8318612, Nov 27, 2012

Filed:

Nov 14, 2008

Appl. No.:

12/937192

Inventors:

Chantal Arena - Mesa AZ, US
Subhash Mahajan - Tempe AZ, US

Assignee:

Soitec - Bernin
Arizona Board of Regents for and on behalf of Arizona State University - Scottsdale AZ

International Classification:

H01L 21/469

US Classification:

438762, 438758, 438759, 438761, 438765, 438767, 438778, 438779, 257 76, 257615, 257E21097

Abstract:

The invention provides methods which can be applied during the epitaxial growth of two or more layers of Group III-nitride semiconductor materials so that the qualities of successive layer are successively improved. In preferred embodiments, surface defects interact with a protective layer of a protective material to form amorphous complex regions capable of preventing the further propagation of defects and dislocations. The invention also includes semiconductor structures fabricated by these methods.

US Patent:

8377802, Feb 19, 2013

Filed:

Mar 23, 2011

Appl. No.:

13/069900

Inventors:

Ed Lindow - Scottsdale AZ, US
Chantal Arena - Mesa AZ, US
Ronald Bertram - Mesa AZ, US
Ranjan Datta - Bangalore, IN
Subhash Mahajan - Tempe AZ, US

Assignee:

Soitec - Bernin

International Classification:

H01L 21/20

US Classification:

438478, 438 22, 438483, 438 46, 438481

Abstract:

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

US Patent:

8574968, Nov 5, 2013

Filed:

Jul 25, 2008

Appl. No.:

12/180418

Inventors:

Chantal Arena - Mesa AZ, US
Christiaan J. Werkhoven - Gilbert AZ, US
Ed Lindow - Scottsdale AZ, US
Subhash Mahajan - Tempe AZ, US
Ranjan Datta - Tempe AZ, US
Rahul Ajay Trivedi - Tempe AZ, US
Ilsu Han - Tempe AZ, US

Assignee:

Soitec - Bernin
Arizona Board of Regents for and on Behalf of Arizona State University - Scottsdale AZ

International Classification:

H01L 21/82

US Classification:

438129, 257E2104, 257E2109, 438172, 438481

Abstract:

This invention provides methods for fabricating substantially continuous layers of a group III nitride semiconductor material having low defect densities and optionally having a selected crystal polarity. The methods include epitaxial growth nucleating and/or seeding on the upper portions of a plurality of pillars/islands of a group III nitride material that are irregularly arranged on a template structure. The upper portions of the islands have low defect densities and optionally have a selected crystal polarity. The invention also includes template structures having a substantially continuous layer of a masking material through which emerge upper portions of the pillars/islands. The invention also includes such template structures. The invention can be applied to a wide range of semiconductor materials, both elemental semiconductors, e. g. , combinations of Si (silicon) with strained Si (sSi) and/or Ge (germanium), and compound semiconductors, e. g.

US Patent:

20130126896, May 23, 2013

Filed:

Jan 10, 2013

Appl. No.:

13/738406

Inventors:

Ed Lindow - Scottsdale AZ, US
Chantal Arena - Mesa AZ, US
Ronald Bertram - Mesa AZ, US
Ranjan Datta - Bangalore, IN
Subhash Mahajan - Tempe AZ, US

Assignee:

Soitec - Bernin

International Classification:

H01L 29/20

US Classification:

257 76

Abstract:

Embodiments of the invention relate to methods of fabricating semiconductor structures, and to semiconductor structures fabricated by such methods. In some embodiments, the methods may be used to fabricate semiconductor structures of III-V materials, such as InGaN. A semiconductor layer is fabricated by growing sublayers using differing sets of growth conditions to improve the homogeneity of the resulting layer, to improve a surface roughness of the resulting layer, and/or to enable the layer to be grown to an increased thickness without the onset of strain relaxation.

US Patent:

20130234157, Sep 12, 2013

Filed:

Nov 23, 2011

Appl. No.:

13/988996

Inventors:

Chantal Arena - Mesa AZ, US
Ed Lindow - Cornville AZ, US
Subhash Mahajan - El Macero CA, US
Fanyu Meng - Tempe AZ, US

Assignee:

Soitec - Bernin

International Classification:

H01L 21/02
H01L 29/20

US Classification:

257 76, 438478

Abstract:

Embodiments of the invention include methods for forming Group III-nitride semiconductor structure using a halide vapor phase epitaxy (HVPE) process. The methods include forming a continuous Group III-nitride nucleation layer on a surface of a non-native growth substrate, the continuous Group III-nitride nucleation layer concealing the upper surface of the non-native growth substrate. Forming the continuous Group III-nitride nucleation layer may include forming a Group III-nitride layer and thermally treating said Group III-nitride layer. Methods may further include forming a further Group III-nitride layer upon the continuous Group III-nitride nucleation layer.

US Patent:

20140217553, Aug 7, 2014

Filed:

Nov 23, 2011

Appl. No.:

13/989004

Inventors:

Chantal Arena - Mesa AZ, US
Ed Lindow - Cornville AZ, US
Subhash Mahajan - El Macero CA, US
Ilsu Han - Tempe AZ, US

Assignee:

ARIZONA BOARD OF REGENTS FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY - Scottsdale AZ
Soitec - Bernin

International Classification:

H01L 21/02
H01L 29/06

US Classification:

257615, 438483

Abstract:

Methods of depositing III-nitride semiconductor materials on substrates include depositing a layer of III-nitride semiconductor material on a surface of a substrate in a nucleation HVPE process stage to form a nucleation layer having a microstructure comprising at least some amorphous III-nitride semiconductor material. The nucleation layer may be annealed to form crystalline islands of epitaxial nucleation material on the surface of the substrate. The islands of epitaxial nucleation material may be grown and coalesced in a coalescence HVPE process stage to form a nucleation template layer of the epitaxial nucleation material. The nucleation template layer may at least substantially cover the surface of the substrate. Additional III-nitride semiconductor material may be deposited over the nucleation template layer of the epitaxial nucleation material in an additional HVPE process stage. Final and intermediate structures comprising III-nitride semiconductor material are formed by such methods.