Subramanian Vani Ramesh

US Patent:

6388586, May 14, 2002

Filed:

Jul 2, 2001

Appl. No.:

09/897346

Inventors:

Matthew Fischer - Richardson TX
Raghuram Kota - Dallas TX
Thavatchai Makphaibulchoke - Arlington TX
Subramanian Ramesh - Plano TX

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H03M 738

US Classification:

341 51, 341 60, 341 65, 341 67, 341 77, 341 78, 708495, 710 22, 710 52, 710105, 710110, 710311, 710315, 711200, 711220, 712300, 712200, 717 11, 717 5

Abstract:

The bits comprising a computer data structure are reversed rapidly and efficiently using a combination of data partitioning and table look ups. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

US Patent:

6413848, Jul 2, 2002

Filed:

Mar 23, 2000

Appl. No.:

09/534907

Inventors:

Gary K. Giust - Cupertino CA
Ruggero Castagnetti - San Jose CA
Subramanian Ramesh - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2144

US Classification:

438601, 438132, 438281, 257209

Abstract:

Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

US Patent:

6778462, Aug 17, 2004

Filed:

May 8, 2003

Appl. No.:

10/431940

Inventors:

Ruggero Castagnetti - Menlo Park CA
Subramanian Ramesh - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 800

US Classification:

36523005, 365 63

Abstract:

The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows âslicesâ of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

US Patent:

6865614, Mar 8, 2005

Filed:

Jul 2, 2001

Appl. No.:

09/897349

Inventors:

Matthew Fischer - Richardson TX, US
Thavatchai Makphaibulchoke - Arlington TX, US
Subramanian Ramesh - Plano TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F015/16

US Classification:

709246, 717140

Abstract:

Computer data is transferred from a packed to an unpacked data structure in a computer that enforces aligned memory access and for which the associated compiler lacks a compile-time directive to pack data structures. In an exemplary embodiment, the invention is employed in the pre-processing of Advanced Configuration and Power Interface (ACPI) tables stored in little-endian format for use by a big-endian operating system.

US Patent:

6934174, Aug 23, 2005

Filed:

Sep 3, 2003

Appl. No.:

10/655053

Inventors:

Ruggero Castagnetti - Menlo Park CA, US
Ramnath Venkatraman - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C005/02

US Classification:

365 51, 365 63

Abstract:

A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

US Patent:

6963970, Nov 8, 2005

Filed:

Apr 29, 2002

Appl. No.:

10/136580

Inventors:

Bradley Culter - Dallas TX, US
Subramanian Ramesh - Plano TX, US
Matthew Fischer - Richardson TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F009/00
G06F009/24
G06F013/24

US Classification:

713 1, 713 2, 710260

Abstract:

A system and method for implementing a fast reset of a computer system is described. In one implementation, the fast reset is implemented by adding a new ResetType to the EFIResetSystem( ) function. In particular, a third ResetType, i. e. , “EfiResetFast” (FAST option), is added, which is passed as a parameter when calling the EFIResetSystem( ) function. In another implementation, the fast reset is implemented using a new EFI function, referred to herein as “EFIResetFast( )”. In either implementation, in response to a fast reset, the firmware skips several steps typically performed, including some of the core firmware construction, single cell initialization, memory testing, memory re-initialization, and partition creation, and proceeds directly to transfer of control of the platform to a software interface disposed between an OS and firmware.

US Patent:

6977512, Dec 20, 2005

Filed:

Dec 4, 2003

Appl. No.:

10/727719

Inventors:

Franklin Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R027/08
G01R031/26

US Classification:

324691, 324765, 324766

Abstract:

Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

US Patent:

6978407, Dec 20, 2005

Filed:

May 27, 2003

Appl. No.:

10/445437

Inventors:

Franklin L. Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C029/00

US Classification:

714721, 714732

Abstract:

A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.