Subramanian A Ramesh

US Patent:

6413848, Jul 2, 2002

Filed:

Mar 23, 2000

Appl. No.:

09/534907

Inventors:

Gary K. Giust - Cupertino CA
Ruggero Castagnetti - San Jose CA
Subramanian Ramesh - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2144

US Classification:

438601, 438132, 438281, 257209

Abstract:

Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned anti-reflective dielectric coatings. The self-alignment allows the size location of the break point to be less sensitive to the laser beam size and alignment. This has several advantages including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less timely, which increases throughput in fabrication.

US Patent:

6778462, Aug 17, 2004

Filed:

May 8, 2003

Appl. No.:

10/431940

Inventors:

Ruggero Castagnetti - Menlo Park CA
Subramanian Ramesh - Cupertino CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 800

US Classification:

36523005, 365 63

Abstract:

The present invention provides a method and apparatus for providing dual-port capability to an SRAM array. The internal nodes of two single-port memory cells are connected to each other through metal-layer programming to form a dual-port memory cell. In a preferred embodiment, a split word line design is used for each single-port memory cell, to facilitate dual-port memory access while minimizing the need for IC layout space. An additional benefit of the present invention is that it allows âslicesâ of a memory array to be converted into dual-port memory, so as to allow both single-port and dual-port memory cells in the same memory array.

US Patent:

6934174, Aug 23, 2005

Filed:

Sep 3, 2003

Appl. No.:

10/655053

Inventors:

Ruggero Castagnetti - Menlo Park CA, US
Ramnath Venkatraman - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C005/02

US Classification:

365 51, 365 63

Abstract:

A method and system for reconfiguring a memory array is disclosed. Initially, the cells in the memory array are patterned with substantially the same structure up to a predefined layer. Thereafter, the memory array is reconfigured by patterning the cells above the predefined layer such that a first plurality of cells function as memory cells, and a second plurality of cells are patterned as a dummy row or column that function as a breakpoint for the memory array.

US Patent:

6977512, Dec 20, 2005

Filed:

Dec 4, 2003

Appl. No.:

10/727719

Inventors:

Franklin Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G01R027/08
G01R031/26

US Classification:

324691, 324765, 324766

Abstract:

Test structures are provided for accurately quantifying shared contact resistance. The test structures are built based upon an actual memory cell, which is self-aligning to allow shared contact chains through an array of test cells. A main array of test cells is built to provide a chain of shared contact resistance. Using the main array of test cells, a resistance in the shared contact chain may be measured. Supplemental arrays of test cells is built to provide a chain of poly side resistance, a chain of island side resistance, a chain of island connection line resistance, and a chain of poly connection resistance. A tester measures resistance using the test structures and uses the values to accurately determine shared contact resistance.

US Patent:

6978407, Dec 20, 2005

Filed:

May 27, 2003

Appl. No.:

10/445437

Inventors:

Franklin L. Duan - San Jose CA, US
Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C029/00

US Classification:

714721, 714732

Abstract:

A self-aligning memory cell design is provided to allow testing of transistors in every cell of a memory circuit. A test array of these cells is fabricated with contact pads in each cell for specific components in the cell. Then, metal lines are provided to couple the contact pads in the test array. The whole test array is then probed via these metal lines. Tests may then be performed to detect random and systematic transistor degradation electrically for all cells in the circuit. Different components in the memory design may be tested by providing contact pads for the components of interest and providing metal lines coupling the contact pads.

US Patent:

6980462, Dec 27, 2005

Filed:

Nov 18, 2003

Appl. No.:

10/715929

Inventors:

Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US
Ramnath Venkatraman - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C011/00

US Classification:

365154, 365156, 36523006

Abstract:

An improved memory cell architecture is provided herein for reducing, or altogether eliminating, chip-level routing congestion in System-on-Chip environments. Though only a few embodiments are provided herein, features common to the described embodiments include: the formation of bitlines in a lower-level metallization layer of the memory array, and the use of word lines and ground supply lines, both formed in inter-level metallization layer(s) of the memory array, for effective shielding of the bitlines against routing signals in the chip-level routing layer.

US Patent:

7006369, Feb 28, 2006

Filed:

Aug 27, 2003

Appl. No.:

10/650192

Inventors:

Ramnath Venkatraman - San Jose CA, US
Rugger Castagnetti - Menlo Park CA, US
Subramanian Ramesh - Cupertino CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 5/06
G11C 11/40

US Classification:

365 63, 365154, 365156, 36518904, 36523005, 257903, 257E27099

Abstract:

The present invention provides a method and apparatus for reconfiguring a memory array. Aspects of the present invention include fabricating the memory array as at least one row of single-port cells up to a first metal layer. A split word line having first and second word lines is coupled to the single-port cells in each row, wherein the first word line is patterned in the first metal layer, and the second word line is patterned in a second metal layer. The split word line is further coupled to a spacer cell in the row. The method and apparatus further include programming the memory array into custom configurations based on whether the first and second word lines are connected over the spacer cell, or whether the first and second word lines are left unconnected.

US Patent:

7006370, Feb 28, 2006

Filed:

Nov 18, 2003

Appl. No.:

10/716259

Inventors:

Subramanian Ramesh - Cupertino CA, US
Ruggero Castagnetti - Menlo Park CA, US
Ramnath Venkatraman - San Jose CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G11C 5/06

US Classification:

365 63

Abstract:

A memory cell architecture is provided herein for increasing memory speed, performance and robustness within a highly compact memory cell layout. Though only a few embodiments are provided herein, a feature common to all embodiments includes a novel means for sharing one or more contact structures between vertically adjacent memory cells. In particular, one or more contact structures may be shared unequally between two vertically adjacent memory cells for reducing a vertical dimension, or length, of the memory cell. Other features are disclosed for producing the highly compact memory cell layout. The various features of the present invention may be combined to produce high-performance, high-density memory arrays.