Hgst, A Western Digital Company Feb 2013 - Nov 2014
Senior Engineer
L&T Infotech Dec 2010 - Sep 2012
Senior Verification Engineer
Wipro Technologies Jan 2008 - Dec 2010
Project Engineer
Education:
Anna University 2003 - 2007
Bachelor of Engineering, Bachelors, Communications, Engineering, Electronics
Skills:
Functional Verification Verilog System Verilog Open Verification Methodology Uvm Assembly Language Systemverilog Asic Debugging C
L&T Infotech Chennai, Tamil Nadu Dec 2010 to Sep 2012 Senior Verification EngineerWipro Technologies Bangalore, Karnataka Jan 2008 to Dec 2010 Verification Engineer
Education:
Hindustan College of Engineering Chennai, Tamil Nadu 2007 Bachelor of Engineering in Electronics and CommunicationRaj matriculation Higher Secondary School Mayiladuthurai,Tamil Nadu,India 2003 BiologyHigh School & Matric Mayiladuthurai, Tamil Nadu, IN
Skills:
System verilog - methodology such as OVM, UVM , Verilog