Sumanth K Gururajarao

US Patent:

6989702, Jan 24, 2006

Filed:

Jul 3, 2003

Appl. No.:

10/613271

Inventors:

Uming Ko - Plano TX, US
David B. Scott - Plano TX, US
Sumanth Gururajarao - Dallas TX, US
Hugh T. Mair - Fairview TX, US
Peter H. Cumming - Yatton Keynell, GB
Franck Dahan - Nice, FR

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/289
H03K 3/356

US Classification:

327203, 327208, 327218

Abstract:

State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M–M; M–M) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to anode (N) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vtransistors (M, M, M and M; M, M, M and M) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.

US Patent:

7091766, Aug 15, 2006

Filed:

Jul 3, 2003

Appl. No.:

10/616207

Inventors:

Uming Ko - Plano TX, US
David B. Scott - Plano TX, US
Sumanth Gururajarao - Dallas TX, US
Hugh Mair - Fairview TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 3/12
H03K 3/37
H03K 3/286
H03K 3/356

US Classification:

327218, 327206, 327208

Abstract:

State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M−M; M−M) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a “don't care” signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vtransistors (M, M, M and M; M, M, M and M) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.

US Patent:

7327185, Feb 5, 2008

Filed:

Nov 1, 2005

Appl. No.:

11/264404

Inventors:

Hugh Mair - Fairview TX, US
Sumanth Gururajarao - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G05F 1/575

US Classification:

327540, 327544, 365227, 700298

Abstract:

An electronic system comprises a plurality of circuit paths. Each path in the plurality of circuit paths is coupled to receive a system voltage from a voltage supply. The system further comprises a first circuit for providing a first value indicating a first potential capability of operational speed of at least one path in the plurality of circuit paths and a second circuit for providing a second value for indicating a second potential capability of operational speed of the at least one path in the plurality of circuit paths. The system further comprises circuitry for adjusting the system voltage, as provided by the voltage supply, in response to a relation between the first value and the second value.

US Patent:

7477551, Jan 13, 2009

Filed:

Nov 8, 2006

Appl. No.:

11/594602

Inventors:

Radu Avramescu - Frisco TX, US
Sumanth Gururajarao - Dallas TX, US
Hugh Thomas Mair - Fairview TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 7/00

US Classification:

36518902, 36523002, 36518903, 36518904, 36518915, 36518916, 36518908

Abstract:

One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

US Patent:

7483819, Jan 27, 2009

Filed:

Dec 7, 2004

Appl. No.:

10/904973

Inventors:

Girishankar Gurumurthy - Chennai, IN
Shitanshu Krishnachandra Tiwari - Vasai(W), IN
Hugh Thomas Mair - Fairview TX, US
Sumanth K Gururajarao - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 17/10

US Classification:

703 2, 703 14

Abstract:

Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.

US Patent:

7564077, Jul 21, 2009

Filed:

May 7, 2007

Appl. No.:

11/745250

Inventors:

Uming Ko - Plano TX, US
Dharin Shah - Bangalore, IN
Senthil Sundaramoorthy - Bangalore, IN
Girishankar Gurumurthy - Chennai, IN
Sumanth Gururajarao - Dallas TX, US
Rolf Lagerquist - Richardson TX, US
Clive Bittlestone - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 27/10
H01L 29/73

US Classification:

257206, 257204, 257E27108

Abstract:

An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.

US Patent:

7622955, Nov 24, 2009

Filed:

Apr 17, 2008

Appl. No.:

12/104580

Inventors:

Sumanth Katte Gururajarao - Dallas TX, US
Hugh T. Mair - Fairview TX, US
Alice Wang - Allen TX, US
Uming U. Ko - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03K 19/094

US Classification:

326 68, 326 21, 326 46

Abstract:

An apparatus for providing active mode power reduction for circuits having data retention includes a master slave flip flop (MSFF) for latching a data input. An output level shifter (OLS), coupled to the MSFF, retains the data input in response to the MSFF being operable in an active power saving mode (APSM) to reduce power. The OLS operating in the APSM provides a level shifter output having a configurable voltage, thereby providing output isolation. A change in an operating mode of the MSFF between an active mode and the APSM is independent of a retention (RET) mode input.

US Patent:

7630270, Dec 8, 2009

Filed:

Aug 20, 2007

Appl. No.:

11/841310

Inventors:

Uming Ko - Plano TX, US
Gordon Gammie - Plano TX, US
Sumanth K. Gururajarao - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G11C 5/14

US Classification:

365227, 365226, 365229

Abstract:

The present disclosure provides a dual-mode voltage controller, a method of supplying voltage to SRAM periphery circuits and an integrated circuit. In one embodiment, the dual-mode voltage controller is for use with an SRAM array and includes a voltage switching unit connected to a digital core voltage and an SRAM array voltage to form a structure capable of switching at least one SRAM periphery circuit between the digital core voltage and the SRAM array voltage.