Sumit Dasgupta

US Patent:

47363193, Apr 5, 1988

Filed:

May 15, 1985

Appl. No.:

6/734304

Inventors:

Sumit DasGupta - Wappingers Falls NY
John M. Hancock - Poughkeepsie NY
James H. Kukula - Poughkeepsie NY
Roger E. Peo - Poughkeepsie NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

G06F 1324

US Classification:

364200

Abstract:

A multiprocessing system has a plurality of processors each having a unique interrupt. An executive processor issues interrupt requests over a global bus having a plurality of interrupt lines. A plurality of bus interface systems are each connected to a different interrupt line in the global bus and to a cell bus. A master cell processor and a plurality of slave cell processors are connected to different interrupt lines in the cell bus. All interrupt requests to a cell go first to the master cell processor and then to a slave processor as appropriate.

US Patent:

57870985, Jul 28, 1998

Filed:

Jul 29, 1996

Appl. No.:

8/688067

Inventors:

Sumit DasGupta - Austin TX
Kris Venkatraman Srikrishnan - Wappingers Falls NY
Ronald Gene Walther - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

371 223

Abstract:

A system and method for evaluating solder ball connections to a flip-chip or the like integrated circuit device through an extension of boundary scan testing circuits and techniques. The existence, size, and connective efficacy of solder balls deposited on pads are indirectly verified through the inclusion of a boundary scan driver and receiver with each pad. The respective drivers and receivers are connected to the complementing sections of a segmented pad metallurgy. The formation of a correct size solder ball connects the driver and receiver to allow boundary scan verification of all the electrical connections in the path. Thereby, low contact testing can be used to verify the integrity of the integrated circuit as well as any solder ball type die (chip) output contacts.

US Patent:

42939194, Oct 6, 1981

Filed:

Aug 13, 1979

Appl. No.:

6/066130

Inventors:

Sumit Dasgupta - Wappingers Falls NY
Prabhakar Goel - Poughkeepsie NY
Thomas W. Williams - Longmont CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 748
G06F 1100
H03K 2330

US Classification:

364716

Abstract:

One of the significant features of the invention, as in U. S. Pat. No. 3,783,254, is the implementation of shift register latches as basic building blocks in a logic organization and system with combinational logic networks which provide the excitation for the shift register latches. These shift register latches in the invention as well as in the patent contain a pair of latches where one is a "master" latch and another a "slave". The structure in the patent requires the "master" and "slave" latches to be part of the shift register for scan-in/scan-out. However, only the "master" may be set with data from the logic system surrounding it while the "slave" may only be set with data which previously resided in the related "master" latch. Thus, in those logic organizations where only the "master" latch output is required, the usefulness of the "slave" latch is limited to scan-in/scan-out. In the shift register latch of the invention, the "slave" latch must be set with the data that resided in the related "master" latch during scan-in/scan-out.

US Patent:

44083360, Oct 4, 1983

Filed:

May 4, 1981

Appl. No.:

6/259878

Inventors:

Sumit DasGupta - Wappingers Falls NY

Assignee:

International Business Machines Corp. - Armonk NY

International Classification:

H03K 2308

US Classification:

377 34

Abstract:

A plurality of two stage Gray code counters are connected in series to generate a multiple bit pseudo Gray code count C. sub. 0, C. sub. 1,. . . , C. sub. 7. A binary count B. sub. 0, B. sub. 1,. . . , B. sub. 7 is then generated by using the odd subscripted bits C. sub. 1, C. sub. 3, C. sub. 5, C. sub. 7 of the pseudo Gray code as the binary count bits B. sub. 1, B. sub. 3, B. sub. 5, B. sub. 7 and generating the even subscripted bits of the binary count B. sub. 0, B. sub. 2, B. sub. 4, B. sub. 6 by Exclusive ORing the odd and even position counts of each two stage Gray code counter together in Exclusive OR circuits.

US Patent:

45090084, Apr 2, 1985

Filed:

Apr 10, 1984

Appl. No.:

6/598638

Inventors:

Sumit DasGupta - Wappingers Falls NY
Matthew C. Graf - Highland NY
Robert A. Rasmussen - LaGrangeville NY
Thomas W. Williams - Boulder CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

324 73R

Abstract:

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time.

US Patent:

45033862, Mar 5, 1985

Filed:

Apr 20, 1982

Appl. No.:

6/370214

Inventors:

Sumit DasGupta - Wappingers Falls NY
Matthew C. Graf - Highland NY
Robert A. Rasmussen - LaGrangeville NY
Thomas W. Williams - Boulder CO

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 3128

US Classification:

324 73R

Abstract:

Disclosed is a design discipline, or approach, in the form of circuitry and a test method, or methodology which obviates the problems of the prior art and allows testing of each individual chip and interchip connections of a plurality of interconnected chips contained on or within a high density packaging structure. This testing is accomplished without the need for and utilization of test equipment having a precision probe and a high precision step and repeat mechanism. CPA is a method and circuit design discipline that, where followed, will result in a testable multichip package given that each logical component is testable and the design is synchronous in nature. The CPA discipline is able to accomplish this by making use of shift register latches on the chips or functional island periphery. These latches are used to indirectly observe and/or control the synchronous network, in many ways replicating the stuckfault test environment under which tests were generated at the lower subcomponent level of assembly. One method, full CPA, offers the ability to apply these tests to all full CPA chips on the multichip package simultaneously or in unison, thus reducing manufacturing tester time.