Sung M Cho

US Patent:

8298949, Oct 30, 2012

Filed:

Jan 7, 2009

Appl. No.:

12/350060

Inventors:

Qinghua Zhong - Fremont CA, US
Sung Cho - Fremont CA, US
Gowri Kamarthy - Pleasanton CA, US
Linda Braly - Oakland CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/311

US Classification:

438696, 438694, 438723, 438770, 438771

Abstract:

A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.

US Patent:

20090022870, Jan 22, 2009

Filed:

Jul 20, 2007

Appl. No.:

11/880078

Inventors:

In Bong Cho - Los Angeles CA, US
Sung Il Cho - Los Angeles CA, US
Jinny Aliya Cho - Los Angeles CA, US
Sung In Cho - Los Angeles CA, US

International Classification:

A23L 1/312

US Classification:

426574

Abstract:

A method of manufacturing a gelatin shape collagen food, which contains a tendon structure therein, is provided. The method is comprised of: 1) boil tendons from a cow in water for 90 minutes, 2) quench the tendon with cold water at 15 C., 3) rip off meats from the tendons, 4) slice the tendons in a shape with a 5 mm thickness, 1 cm width and 10 cm length. At the same time 5) boil cow's pettitoe in water for one hour, 6) rip off skin of the cow pettitoe and remove fats by hand, 7) boil the cow's pettitoe again in water for 30 minutes to remove residual fat, 8) mix the sliced tendons and ripped off pettitoe in water in 1:1:4 volume ratios, add caramel drop, gelatin powders and apple cider, 9) boil down the mixtures prepared in the eighth step slowly for 1.5 hours, 10) put the mixture in a mold and quench as soon as possible, 11) dry out the gelatin structure by blowing air at room temperature for four hours, and 12) cut the gelatin structure into desired size.

US Patent:

20130025785, Jan 31, 2013

Filed:

Sep 27, 2012

Appl. No.:

13/629235

Inventors:

Lam Research Corporation - Fremont CA, US
Sung Cho - Fremont CA, US
Gowri Kamarthy - Pleasanton CA, US
Linda Braly - Oakland CA, US

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H01L 21/3065

US Classification:

15634524, 15634528

Abstract:

An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.

US Patent:

55599664, Sep 24, 1996

Filed:

Sep 13, 1993

Appl. No.:

8/120292

Inventors:

Sung S. Cho - Sunnyvale CA
Eugene P. Matter - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03K 190175
H02J 104
H02J 318
G06F 1300

US Classification:

395285

Abstract:

A computer system having switchable 3. 3 volt or 5 volt interface bus. The computer system includes a microprocessor and multiple peripheral integrated circuits. The microprocessor and other peripheral integrated circuits are coupled to the interface bus through groups of buffers on the integrated circuits. These buffers operate at the voltage level of the interface bus and include voltage translation circuitry for translating interface bus signals to voltage level at which the core logic of the microprocessor and other peripheral chips operate.

US Patent:

55354203, Jul 9, 1996

Filed:

Dec 14, 1994

Appl. No.:

8/356131

Inventors:

James Kardach - San Jose CA
Sung S. Cho - Sunnyvale CA
Nicholas B. Peterson - San Jose CA
Thomas R. Lane - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1324

US Classification:

395868

Abstract:

A computer architecture which provides for the dynamic configuration of peripheral interrupts. A global router is implemented for mapping interrupts received over a multiple-line shared interrupt bus to correspond to system standard IRQ interrupt signals for a programable interrupt controller (PIC). The global router may configure interrupts to be both level sensitive and edge-triggered interrupts as well as being sharable among multiple devices. The global router further provides its interrupts to a shared interrupt bus which may receive other system interrupts for propagation to the computer system's PIC. The global router provides a centrally located motherboard resource that provides a totally flexible interrupt configuration scheme.

US Patent:

58623892, Jan 19, 1999

Filed:

Jan 3, 1997

Appl. No.:

8/778516

Inventors:

James P. Kardach - Saratoga CA
Sung Soo Cho - Sunnyvale CA
Jayesh M. Joshi - Santa Clara CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1324

US Classification:

395739

Abstract:

A circuit for selectively invoking a particular interrupt service routine to handle a particular interrupt request. The present invention includes a programmable register with one or more bits per interrupt request input. The present invention also includes interrupt selection logic which outputs a particular interrupt in response to an interrupt request input and data stored in the programmable register. The interrupt then invokes the associated interrupt service routine to handle the interrupt request. The present invention is used to choose the interrupt service routine to handle a particular interrupt request from any source within the computer system in any computer system operating mode.

US Patent:

60553723, Apr 25, 2000

Filed:

May 1, 1997

Appl. No.:

8/845634

Inventors:

James Kardach - San Jose CA
Sung Soo Cho - Sunnyvale CA
Nicholas B. Peterson - San Jose CA
Thomas R Lane - San Jose CA
Jayesh M. Joshi - Santa Clara CA
Neil Songer - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 946

US Classification:

395734

Abstract:

A serial interrupt bus protocol is implemented in which any number of peripherals in a computer system may signal any predetermined interrupt signals to the system's interrupt controller without requiring a dedicated pin for each possible interrupt. Each peripheral implemented on the serial interrupt bus incorporates state machine logic for cycling through possible interrupt states. The peripherals are daisy chained beginning and ending with a serial interrupt controller which follows the same state machine logic as the system peripherals. When the serial interrupt controller receives an active interrupt signal, it determines which interrupt signal to provide to the system's interrupt controller based on the interrupt state of the interrupt controller state machine logic. Peripherals on a secondary serial interrupt bus may be daisy chained with peripherals on a primary system interrupt bus through a system interrupt bridge which also includes state machine logic for following the same state diagram as the system peripherals.

US Patent:

52768880, Jan 4, 1994

Filed:

Oct 22, 1992

Appl. No.:

7/964788

Inventors:

James Kardach - San Jose CA
Gregory Mathews - Cupertino CA
Cau Nguyen - Milpitas CA
Sung S. Cho - Sunnyvale CA
Kameswaran Sivamani - Sunnyvale CA
David Vannier - Cupertino CA
Shing Wong - Cupertino CA
Edward Zager - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 946
G06F 1200

US Classification:

395725

Abstract:

A transparent system interrupt is invoked by the assertion of an electrical signal at an external pin of a microprocessor CPU chip. Upon assertion of this interrupt, the CPU begins program execution in a dedicated RAM area that is inaccessible both to the operating system and all application programs. A set of instructions, which may be unique to the system in which the CPU chip is installed, services the interrupt. Typically, the state of the CPU and associated components in the system immediately prior to assertion of the interrupt will be saved into the dedicated RAM area by the interrupt service routine. Recovery from the interrupt is accomplished upon recognition of an external event that invokes a RESUME instruction causing the CPU and associated components to be restored to exactly the same state that existed prior to the interrupt and in a manner entirely transparent to any program executing at the time of the interrupt.