Sung Y Chung

US Patent:

6446230, Sep 3, 2002

Filed:

Sep 14, 1998

Appl. No.:

09/152940

Inventors:

Sung Soo Chung - San Jose CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

714726, 714727

Abstract:

A mechanism for enabling compliance with the IEEE boundary-scan standard 1149. 1 includes, in a first preferred embodiment, a compliance enabler working with non-compliant embedded boundary-scan cells to enable a Device Under Test (DUT) to function as an IEEE-standard-compliant part, thus allowing full utilization of existing test tool generation and operation of the IEEE standard. The enabler is preferably provided separately from boundary scan-cells embedded in core logic designs. The enabler includes a Test Access Port (TAP) controller and related decoding circuits to generate necessary compliance signals based on various conventional TAP controller variables and instruction functions. The embedded boundary-scan cells preferably include an internal scan cell architecture. In a second embodiment, a second enabler works with a TAP emulator to allow testing of TAP-less DUTs.

US Patent:

6560739, May 6, 2003

Filed:

Jun 27, 2002

Appl. No.:

10/185166

Inventors:

Sung Soo Chung - San Jose CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 3128

US Classification:

714726, 714727

Abstract:

A mechanism for enabling compliance with the IEEE boundary-scan standard 1149. 1 includes, in a first preferred embodiment, a compliance enabler working with non-compliant embedded boundary-scan cells to enable a Device Under Test (DUT) to function as an IEEE-standard-compliant part, thus allowing full utilization of existing test tool generation and operation of the IEEE standard. The enabler is preferably provided separately from boundary scan-cells embedded in core logic designs. The enabler includes a Test Access Port (TAP) controller and related decoding circuits to generate necessary compliance signals based on various conventional TAP controller variables and instruction functions. The embedded boundary-scan cells preferably include an internal scan cell architecture. In a second embodiment, a second enabler works with a TAP emulator to allow testing of TAP-less DUTs.

US Patent:

6934921, Aug 23, 2005

Filed:

Jan 4, 2002

Appl. No.:

10/041109

Inventors:

Xinli Gu - Sunnyvale CA, US
Sung Soo Chung - San Jose CA, US
Frank Tsang - Fremont CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F017/50
G01R031/28

US Classification:

716 6, 714733

Abstract:

Resolving timing violations introduced by a logic built-in self test (LBIST) sub-circuit formed within an underlying integrated circuit includes analyzing a circuit path-list corresponding to the integrated circuit for timing violations and generating a circuit timing violations analysis output; generating a first LBIST/circuit path-list based on the circuit path-list and an LBIST path-list corresponding to the LBIST sub-circuit; analyzing the first LBIST/circuit path-list for timing violations and generating an LBIST/circuit timing violations analysis output; comparing the LBIST/circuit timing violations analysis output with the circuit timing violations analysis output; generating an LBIST/circuit constraint file based on the comparison and predetermined protocols; and generating a second LBIST/circuit path-list based on the circuit path-list, the LBIST path-list and the constraints file. In this way, timing problems are quickly and efficiently resolved.

US Patent:

7089463, Aug 8, 2006

Filed:

Feb 20, 2002

Appl. No.:

10/080145

Inventors:

Sang Hyeon Baeg - Cupertino CA, US
Sung Soo Chung - San Jose CA, US

Assignee:

Cisco Technology Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714712, 714709, 714727, 714821, 702117

Abstract:

A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149. 1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

US Patent:

7089470, Aug 8, 2006

Filed:

Apr 11, 2003

Appl. No.:

10/412192

Inventors:

Sang Hyeon Baeg - Cupertino CA, US
Sung Soo Chung - San Jose CA, US
Hongshin Jun - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/28
G06F 11/00

US Classification:

714727, 714738

Abstract:

Programmable test pattern driver and capture mechanisms for boundary scan cluster or functional block testing. A boundary scan test system includes at least one device under test. The device may include a Test Access Port (TAP) controller, a plurality of output AC boundary scan cells (BSCs), and a plurality of input AC BSCs. The device may further include a programmable AC_Pattern_Source signal generator configured to produce AC signal patterns that selectively remain unchanged for at least one cycle before and after an original capture cycle location, a programmable AC_Sync signal generator configured to independently control the AC_Sync signal to lead or lag an original cycle location at full cycle increments, a programmable phase controller configured to independently control either the rising or falling edge aligned AC_Pattern_Clock signal or AC_Counter_Clock signal, and an AC_Test_Clock signal switcher configured to selectively utilize one of a plurality of clock signals including a TCK signal.

US Patent:

7174492, Feb 6, 2007

Filed:

Apr 12, 2001

Appl. No.:

09/834506

Inventors:

Sung Soo Chung - San Jose CA, US
Sang Hyeon Baeg - Cupertino CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714727, 714738

Abstract:

Testing AC coupled interconnects using boundary scan test methodology. Specially designed AC boundary scan cells and boundary scan logic are used. These are compatible with IEEE Standard 1149. 1 testing. An AC_EXTEST method is used to determine the reliability of the AC coupled interconnections. The method includes preloading the test stimulus, initiating the AC_EXTEST instruction, executing the instruction, transferring the instruction results, and evaluating the results. During the test, the TAP controllers of both the driving and receiving ICs are held in the Run-Test/Idle state for the time required to complete execution of the instruction. During this time, the driving IC is applying the AC test stimulus to the interconnections and the receiving IC is sampling the signal. The test may be repeated with different test data and may be run together with a DC EXTEST method to determine the reliability of both the AC and the DC coupled interconnections independently.

US Patent:

7487412, Feb 3, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/450028

Inventors:

Sang Hyeon Baeg - Cupertino CA, US
Sung Soo Chung - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714712, 714 25, 714 43, 714 56, 714726, 714727, 714740, 714734, 714821, 702117, 327 1, 324512

Abstract:

A boundary scan test system including a transmitter and a receiver. The system performs DC and AC boundary scan testing of the interconnections between devices. The system addresses fault masking that can occur during testing. Of concern are AC coupled interconnections while providing IEEE 1149. 1 DC test compatibility. The test receiver includes an input test buffer and an interface mechanism. The input test buffer has a built-in null detection capability. The interface mechanism includes a technology mapper, one or more detectors, and an integrator. The receiver provides at least partial, if not complete, coverage for at least one of five fault syndromes that can result from single defect conditions in the system.

US Patent:

7536617, May 19, 2009

Filed:

Apr 12, 2005

Appl. No.:

11/103877

Inventors:

Sung Soo Chung - San Jose CA, US
Heong Kim - San Jose CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G01R 31/28

US Classification:

714731, 327158, 327141, 327116

Abstract:

A system and method for programmable in-situ launch and capture clock generation is provided. The system provides an efficient and improved manner for delay and signal transition fault testing in electronic circuits. The system comprises i) an in-situ delay clock generator for generating one or more clocks; ii) a pulse Programmable Selection Generator (PSG) which can be either a pulse PSG and/or an expanded pulse PSG for generating the sequence in which the clocks are to be selected, the clocks being selected with a delay; and iii) a multiplexer for selecting the plurality of clocks, based on the generated sequence, the selected clocks being used for generating the launch and capture clocks.