Sunil Gupta

US Patent:

7405586, Jul 29, 2008

Filed:

Mar 20, 2006

Appl. No.:

11/385131

Inventors:

Sunil Gupta - Austin TX, US
Reed Linde - El Dorado Hills CA, US
Rich Fackenthal - Carmichael CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 31/26

US Classification:

324765, 324763, 714734

Abstract:

An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.

US Patent:

7693244, Apr 6, 2010

Filed:

Mar 31, 2006

Appl. No.:

11/394605

Inventors:

Sunil Gupta - Austin TX, US
Rodney R. Rozman - Placerville CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/00

US Classification:

375355, 375326

Abstract:

A system, apparatus, method and article to encode, clock recover, and sample data bits are described. The apparatus may include a pulsed digital module comprising a first clock input, a first data input, a data output, and a reset input. The first clock input to receive an encoded signal from a single-wire. The encoded signal comprising a serial bit sequence comprising a clock signal embedded encoded data bit. The pulsed digital module to capture an edge of the encoded signal at the first clock input in accordance with a logic level coupled to the first data input. A delay module comprising a delay input is coupled to the data output and a delay output is coupled to the reset input. The delay module to delay the captured edge by a predetermined period and to generate a delay signal from the delay output after the predetermined period. The pulsed digital module is to generate a first clock edge of the sampling clock at the data output after the predetermined period. An apparatus, system, and method to embed a sampling clock signal via an encoded signal comprising n bits and to transmit the encoded signal to a single-wire as a serial bit sequence of n bits.

US Patent:

20200395051, Dec 17, 2020

Filed:

Jun 14, 2019

Appl. No.:

16/442208

Inventors:

- San Diego CA, US
Sunil GUPTA - San Diego CA, US

International Classification:

G11C 5/06
H01L 25/18

Abstract:

An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.