Suresh D Patel

US Patent:

47589477, Jul 19, 1988

Filed:

Feb 16, 1984

Appl. No.:

6/580960

Inventors:

Ytzhak Levendel - Naperville IL
Premachandran R. Menon - Naperville IL
Suresh H. Patel - Wheaton IL

Assignee:

American Telephone and Telegraph Company, AT&T Bell Laboratories - Murray Hill NJ

International Classification:

G06F 700

US Classification:

364200

Abstract:

Disclosed is a slave processor (100) for a multiprocessor logic circuit fault simulator. The slave processor has a hardware-based list processor (110) for performing set algebra operations on fault lists (300). The operation of the list processor centers on a characteristic vector (A) that has a bit (360) for each fault number (310) that can appear in a fault list. The bits are implemented in bit locations (210) of a register (201). The list processor also has a second vector (B), implemented in a register (202), whose bit locations form shift register pairs (208) with locations of vector A bits to store values of vector A bits shifted out by entry of new values. The list processor further has two stacks (A, B), implemented in memories (203, 204), for storing fault numbers. As fault numbers of a first fault list are loaded into the list processor, corresponding vector A bits are set, and the fault numbers are pushed onto the stack A. As fault numbers of subsequent fault lists are loaded, corresponding or non-corresponding vector A bits are set or reset, depending upon whether the set operation being performed is union, intersection, or difference.