Takeshi Nogami - Sunnyvale CA Susan H. Chen - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2348
US Classification:
257751, 257762, 257765
Abstract:
A combined interconnect system is formed comprising a Cu or Cu alloy feature electrically connected an Al or Al alloy feature through a composite comprising a first layer containing tantalum and aluminum contacting the Al or Al alloy feature, a second layer containing tantalum nitride, a third layer containing tantalum nitride having an nitrogen content less than that of the second layer, e. g. amorphous tantalum nitride, and a fourth layer comprising tantalum or tantalum nitride having a nitrogen content less than that of the third layer. Embodiments include forming a dual damascene opening in the dielectric layer exposing a lower Al or Al alloy feature, depositing a layer of tantalum in contact with the Al or Al alloy feature, sequentially depositing the second, third and fourth layers, filling the opening with Cu or Cu alloy layer, CMP and heating to diffuse aluminum from the underlying feature into the first tantalum layer.
Semiconductor Device And Method Of Manufacturing Without Damaging Hsq Layer And Metal Pattern
Fei Wang - San Jose CA Simon S. Chan - Saratoga CA Susan Chen - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21302
US Classification:
438712
Abstract:
HSQ is employed as a dielectric layer in manufacturing a high density, multi-metal layer semiconductor device. The degradation of deposited HSQ layers during formation of the semiconductor device, as from photoresist stripping using an O -containing plasma, is avoided by forming first and second dielectric layers on the HSQ layer, forming a photoresist mask on the second dielectric layer and etching to form an opening in the second dielectric layer leaving the first dielectric layer exposed. The first dielectric layer protects the HSQ from degradation during subsequent stripping.
Post-Spacer Etch Surface Treatment For Improved Silicide Formation
Susan H. Chen - Santa Clara CA Simon S. Chan - Saratoga CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 213205
US Classification:
438592, 438774
Abstract:
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices have been reduced or a minimal junction leakage are formed by a salicide process wherein carbonaceous residue on silicon substrate surfaces resulting from reactive plasma etching for sidewall spacer formation is removed prior to salicide processing. Embodiments include forming a sacrificial oxide and removing the sacrificial oxide to remove the carbonaceous residues and anneal out damage to the silicon substrate. Subsequently formed silicide regions on the source and drain regions have improved quality.
Anti-Reflective Coating Used In The Fabrication Of Microcircuit Structures In 0.18 Micron And Smaller Technologies
An anti-reflective coating for use in microcircuit fabrication and specifically using ultraviolet photolithographic processes. A three-layered anti-reflective coating is used to enhance metallization etching in the construction of microcircuits. The coating features a titanium nitride anti-reflective layer sandwiched between two titanium metal layers. The upper titanium layer protects subsequently applied deep ultraviolet photoresists from the deleterious effects of the titanium nitride anti-reflective layer. The unique character of the three layer anti-reflective coating allows the use of an efficient single chamber fabrication process to form the three-layer coating.
Method Of Selectively Controlling Contact Resistance By Controlling Impurity Concentration And Silicide Thickness
Susan H. Chen - Santa Clara CA Paul R. Besser - Sunnyvale CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2128
US Classification:
438583, 438674
Abstract:
Methods are provided that selectively provide various contact resistances based on each individual transistors influence on an overall chip speed during the formation of active regions and silicide layers. In order to provide lower contact resistance to devices which have a critical influence on overall device speed, the active regions of such critical devices are formed with a lower impurity concentration and thicker silicide layers are provided on the active regions. Likewise, for the normal devices which have less or no influence on overall chip speed, thinner silicide layers are provided on the active regions having a higher impurity concentration than the critical devices.
Sidewall Spacer Etch Process For Improved Silicide Formation
Angela T. Hui - Fremont CA Paul R. Besser - Austin TX Susan H. Chen - Santa Clara CA
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 21336
US Classification:
438305, 438586, 438680
Abstract:
Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein silicon substrate surfaces intended to be subjected to ion implantation for source/drain formation are protected from damage resulting from reactive plasma etching of a blanket insulative layer for sidewall spacer formation by leaving a residual thickness of the insulative layer thereon. The residual layer is retained during ion implantation and removed prior to salicide processing to provide an undamaged surface for optimal contact formation thereon. Embodiments include anisotropically plasma etching a major amount of the thickness of the blanket insulative layer during a preselected interval for sidewall spacer formation and removing the residual thickness thereof after source/drain implantation by etching with dilute aqueous HF.
Reverse Mask And Nitride Layer Deposition For Reduction Of Vertical Capacitance Variation In Multi-Layer Metallization Systems
Susan H. Chen - Santa Clara CA Paul R. Besser - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2144
US Classification:
438626, 438618, 438623, 438735
Abstract:
Excessive variation in vertical (i. e. , inter-level) capacitance of multi-level metallization semiconductor devices resulting in poor RC time constants of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated or substantially reduced by selectively providing an etch-resistant masking material at thinner, i. e. , recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second and third dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer, thereby serving as a partial etch stop layer preventing deleterious over-etching of the borderless via.
Reverse Mask And Oxide Layer Deposition For Reduction Of Vertical Capacitance Variation In Multi-Layer Metallization Systems
Susan H. Chen - Santa Clara CA Paul R. Besser - Austin TX
Assignee:
Advanced Micro Devices, Inc. - Sunnyvale CA
International Classification:
H01L 2120
US Classification:
438584, 438622, 438645, 438699
Abstract:
Excessive variation in vertical (i. e. , inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i. e. , recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface. The second and third dielectric layers are selected such that the second dielectric layer etches at a substantially slower rate than the third dielectric layer and thus serves as a partial etch stop layer, thereby preventing deleterious over-etching of the borderless via.
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39200 Liberty St STE A, Fremont, CA 94538
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Susan's Dance Studio Dance Studio/School/Hall
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Motorsport Freaks, Inc MOTORCYCLE PARTS DEALER (E-COMMERCE)
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Susan Chen Managing Director
The University of Texas Investment Management Company
Nov 2011 to 2000 Allocation Analyst, Allocation and Planning DepartmentIvyTutor Center
Sep 2011 to 2000 SAT InstructorLiberty Mutual Insurance Group Boston, MA Jun 2009 to Aug 2009 Product Management Intern, Auto Insurance and Specialty Lines Insurance ProductsTarget Corporation Minneapolis, MN Jun 2008 to Aug 2008 Business Analyst Intern, Merchandising Process and Systems Development
Education:
DUKE UNIVERSITY Durham, NC Aug 2010 to May 2011 Graduate Certificate in Public Policy StudiesSTANFORD UNIVERSITY Stanford, CA 2006 to 2010 Bachelor of Arts in International Relations and Asian American StudiesPEKING UNIVERSITY 2008 Econometrics
David Mitchell, George Pace, Andrew Peter, Jim Barton, David Birdsell, Ralph Herpel, Joann Kneib, Kay Bird, Carl Edwards, Patrick Chambers, Helen Byrnes, Rita Rhoad