Susan G Kearney

US Patent:

49948873, Feb 19, 1991

Filed:

Nov 13, 1987

Appl. No.:

7/120558

Inventors:

Louis N. Hutter - Richardson TX
Mark E. Gibson - Mesquite TX
Jeffrey P. Smith - Plano TX
Shiu-Hang Yan - Richardson TX
Arnold C. Conway - Garland TX
John P. Erdeljac - Plano TX
James D. Goon - Dallas TX
AnhKim Duong - Garland TX
Mary A. Murphy - Richardson TX
Susan S. Kearney - Tully NY

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2702
H01L 2704

US Classification:

357 43

Abstract:

An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.