Susan V Riley

US Patent:

52926869, Mar 8, 1994

Filed:

Dec 18, 1991

Appl. No.:

7/810740

Inventors:

Susan Riley - Gaston OR
Terri L. Clayton - Aloha OR

Assignee:

TriQuint Semiconductor, Inc. - Beaverton OR

International Classification:

H01L 2126

US Classification:

437173

Abstract:

A method of forming substrate vias in a GaAs wafer begins with a GaAs wafer in which all top side processing steps are complete. The top surface of the GaAs wafer includes top surface via contacts, which are in electrical contact with the bottom surface ground plane once the ground vias are complete. A protective layer is formed on the top surface of the wafer to protect the finished integrated circuitry. A portion of the substrate is removed from the bottom surface to achieve a thin layer of substrate material. The bottom surface of the thinned substrate is metalized with a first metal layer. Laser via holes are drilled into the thinned substrate from the bottom surface of the wafer to within a few microns from the top surface metal via contacts. The laser holes are drilled by emitting a controlled number of single pulses over the selected via location. The substrate vias are subsequently wet etched to remove the remaining substrate thickness and the bottom surface of the wafer and the substrate via holes are metalized with a second metal layer.