Suzanne Plummer Plummer

US Patent:

20120124586, May 17, 2012

Filed:

Nov 16, 2010

Appl. No.:

12/947715

Inventors:

Daniel Hopper - Austin TX, US
Suzanne Plummer - Austin TX, US
Christopher D. Bryant - Austin TX, US

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the apparatus. One embodiment of the method includes determining whether a first group, comprising at least one or more instructions, is to be selected from a scheduling queue of a processor for execution using either a first execution mode or a second execution mode. The method also includes, responsive to determining that the first group is to be selected for execution using the second execution mode, preventing selection of the first group until a second group, comprising at least one or more instructions, that entered the scheduling queue prior to the first group is selected for execution.

US Patent:

7093153, Aug 15, 2006

Filed:

Oct 30, 2002

Appl. No.:

10/284763

Inventors:

Richard T. Witek - Austin TX, US
Suzanne Plummer - Austin TX, US
James Joseph Montanaro - Austin TX, US
Stephen Charles Kromer - Austin TX, US
Kathryn Jean Hoover - Austin TX, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 1/08

US Classification:

713600, 713300, 713320, 713322, 713323, 713500, 713602, 327100, 327113, 327297, 710110, 710113, 710117, 710305, 710313, 714 34, 714814

Abstract:

A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.