Tae Ju Ha

US Patent:

8476162, Jul 2, 2013

Filed:

Oct 7, 2011

Appl. No.:

13/269243

Inventors:

Tae Hong Ha - San Jose CA, US
Winsor Lam - San Francisco CA, US
Joung Joo Lee - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/44

US Classification:

438654, 438695, 257E21584

Abstract:

Methods for forming layers on a substrate are provided herein. In some embodiments, methods of forming layers on a substrate disposed in a process chamber may include depositing a barrier layer comprising titanium within one or more features in the substrate; and sputtering a material from a target in the presence of a plasma formed from a process gas by applying a DC power to the target, maintaining a pressure of less than about 500 mTorr within the process chamber, and providing up to about 5000 W of a substrate bias RF power to deposit a seed layer comprising the material atop the barrier layer.

US Patent:

20110315319, Dec 29, 2011

Filed:

Jun 22, 2011

Appl. No.:

13/166213

Inventors:

JOHN C. FORSTER - Mt. View CA, US
TAE HONG HA - San Jose CA, US
MURALI K. NARASIMHAN - San Jose CA, US
XINYU FU - Fremont CA, US
ARVIND SUNDARRAJAN - San Jose CA, US
XIAOXI GUO - Saratoga CA, US

Assignee:

APPLIED MATERIALS, INC. - Santa Clara CA

International Classification:

B08B 5/00

US Classification:

15634529

Abstract:

Apparatus for processing substrates are disclosed herein. In some embodiments, a substrate processing system may include a process chamber having a first volume to receive a plasma and a second volume for processing a substrate; a substrate support disposed in the second volume; and a plasma filter disposed in the process chamber between the first volume and the second volume such that a plasma formed in the first volume can only flow from the first volume to the second volume through the plasma filter. In some embodiments, the substrate processing system includes a process kit coupled to the process chamber, wherein the plasma filter is disposed in the process kit.

US Patent:

20220344275, Oct 27, 2022

Filed:

Jul 6, 2022

Appl. No.:

17/858274

Inventors:

- Santa Clara CA, US
Feng Chen - San Jose CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Lu Chen - Cupertino CA, US
Zhiyuan Wu - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 23/532
H01L 23/522
H01L 21/768

Abstract:

Electronic devices and methods of forming electronic devices using a ruthenium or doped ruthenium liner and cap layer are described. A liner with a ruthenium layer and a cobalt layer is formed on a barrier layer. A conductive fill forms a second conductive line in contact with the first conductive line.

US Patent:

20220336223, Oct 20, 2022

Filed:

Jun 22, 2022

Appl. No.:

17/846155

Inventors:

- Santa Clara CA, US
Xuesong Lu - San Jose CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Andrew Nguyen - San Jose CA, US
Philip A. Kraus - San Jose CA, US
Chung Nang Liu - Foster City CA, US
Hui Sun - San Jose CA, US
Yufei Hu - Fremont CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/311
H01L 21/02
H01J 37/32
H01L 21/683
H01L 21/3105
H01L 21/67
H01L 21/8234

Abstract:

Described is a process to clean up junction interfaces for fabricating semiconductor devices involving forming low-resistance electrical connections between vertically separated regions. An etch can be performed to remove silicon oxide on silicon surface at the bottom of a recessed feature. Described are methods and apparatus for etching up the bottom oxide of a hole or trench while minimizing the effects to the underlying epitaxial layer and to the dielectric layers on the field and the corners of metal gate structures. The method for etching features involves a reaction chamber equipped with a combination of capacitively coupled plasma and inductive coupled plasma. CHFgases and plasma are used to form protection layer, which enables the selectively etching of bottom silicon dioxide by NH—NFplasma. Ideally, silicon oxide on EPI is removed to ensure low-resistance electric contact while the epitaxial layer and field/corner dielectric layers are—etched only minimally or not at all.

US Patent:

20220336227, Oct 20, 2022

Filed:

Jul 5, 2022

Appl. No.:

17/857381

Inventors:

- Santa Clara CA, US
AVGERINOS GELATOS - SCOTTS VALLEY CA, US
TAE HONG HA - SAN JOSE CA, US
XUESONG LU - San Jose CA, US
SZUHENG HO - SUNNYVALE CA, US
WEI LEI - CAMPBELL CA, US
MARK LEE - MOUNTAIN VIEW CA, US
RAYMOND HUNG - Palo Alto CA, US
XIANMIN TANG - SAN JOSE CA, US

International Classification:

H01L 21/3205
H01L 21/285
H01L 21/02
H01L 21/321
C23C 16/02
H01L 21/768
C23C 16/455
C23C 16/06
C23C 16/34
C23C 14/06
C23C 16/56

Abstract:

Methods for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

US Patent:

20220328348, Oct 13, 2022

Filed:

Jun 29, 2022

Appl. No.:

17/853150

Inventors:

- Santa Clara CA, US
Xiangjin Xie - Fremont CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Lu Chen - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/768
C23C 16/455
C23C 16/34

Abstract:

Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.

US Patent:

20220231137, Jul 21, 2022

Filed:

Jan 19, 2021

Appl. No.:

17/152190

Inventors:

- Santa Clara CA, US
Joung Joo Lee - San Jose CA, US
Wenting Hou - San Jose CA, US
Takashi Kuratomi - San Jose CA, US
Avgerinos V. Gelatos - Scotts Valley CA, US
Jianxin Lei - Fremont CA, US
Liqi Wu - San Jose CA, US
Raymond Hoiman Hung - Palo Alto CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 29/417
H01L 21/285
H01L 21/8234

Abstract:

A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

US Patent:

20210407853, Dec 30, 2021

Filed:

Jun 28, 2020

Appl. No.:

16/914416

Inventors:

- Santa Clara CA, US
Xiangjin Xie - Fremont CA, US
Tae Hong Ha - San Jose CA, US
Xianmin Tang - San Jose CA, US
Lu Chen - Cupertino CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/768
C23C 16/34
C23C 16/455

Abstract:

Methods of forming copper interconnects are described. A doped tantalum nitride layer formed on a copper layer on a substrate has a first amount of dopant. The doped tantalum nitride layer is exposed to a plasma comprising one or more of helium or neon to form a treated doped tantalum nitride layer with a decreased amount of dopant. Apparatus for performing the methods are also described.