Tao U Yu

US Patent:

7649932, Jan 19, 2010

Filed:

Nov 30, 2005

Appl. No.:

11/291344

Inventors:

Ping Dong - Cupertino CA, US
Tao Yu - Milpitas CA, US

Assignee:

Microtune (Texas), L.P. - Plano TX

International Classification:

H03H 7/30

US Classification:

375232

Abstract:

In one embodiment of the present invention, a segmented equalizer includes a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v}, wherein n is the index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment.

US Patent:

8027800, Sep 27, 2011

Filed:

Jun 24, 2008

Appl. No.:

12/145407

Inventors:

Ramez Nachman - Santa Clara CA, US
Lei Chen - Cupertino CA, US
Tao Yu - Campbell CA, US

Assignee:

QUALCOMM MEMS Technologies, Inc. - San Diego CA

International Classification:

G01R 31/00

US Classification:

702117, 702 64, 702 81

Abstract:

In some embodiments, each interferometric modulator has a stiction threshold voltage. If a voltage above the stiction threshold voltage is applied to the interferometric modulator, the interferometric modulator enters a stiction state permanently, i. e. , becomes “stuck,” and the interferometric modulator becomes inoperable. Disclosed are apparatuses, methods and computer-readable media for testing a panel of interferometric modulators. A ramped voltage waveform is applied to a plurality of interferometric modulators of the panel. In response to applying the ramped voltage, the stiction threshold voltage is identified. At or above this voltage, the number of stuck interferometric modulators in the panel reaches or exceeds a first threshold number, for example, 50% of the total number of the interferometric modulators constituting the panel. The embodiments can be used to establish stiction benchmark for panel manufacturing processes, to collect data for generating statistical distribution, etc.

US Patent:

8107523, Jan 31, 2012

Filed:

Jan 4, 2010

Appl. No.:

12/651980

Inventors:

Ping Dong - Cupertino CA, US
Tao Yu - Milpitas CA, US

Assignee:

Zoran Corporation - Sunnyvale CA

International Classification:

H04L 27/01

US Classification:

375233

Abstract:

In one embodiment of the present invention, a segmented equalizer includes a plurality of feedforward equalizer segments, each feedforward equalizer segment responsive to delayed samples of an input signal {v}, wherein n is the index of samples, and including a filter block for filtering the delayed samples by using coefficients which are updated based on a step size generated for each equalizer segment.

US Patent:

8108749, Jan 31, 2012

Filed:

Mar 6, 2008

Appl. No.:

12/043798

Inventors:

Jordan Christopher Cookman - San Jose CA, US
Ping Dong - Cupertino CA, US
Tao Yu - Milpitas CA, US

Assignee:

Zoran Corporation - Sunnyvale CA

International Classification:

H03M 13/00

US Classification:

714752, 714758, 375141, 375143, 375144, 375148, 455101

Abstract:

An iterative decoder circuit includes an N number of sub-decoders, N−1 of the sub-decoders each being responsive to a baseband signal from one of M number of signal processing circuits. Each of the N−1 number of sub-decoders includes, an inner delay responsive to a baseband signal provided by a corresponding signal processing circuit for generating an inner delayed signal, a modified decoder that receives the inner delayed signal and generates a set partition signal, some of which have less errors than previous set partition signals. An Nth inner delay is responsive to the baseband signal and provides an Nth inner delayed signal. An Nth modified decoder is responsive to the Nth inner delayed signal and to the set partition signal and provides an output signal, wherein the probability of error of the output signal is reduced by correcting errors in some of the set partition signals.

US Patent:

8135058, Mar 13, 2012

Filed:

Oct 10, 2008

Appl. No.:

12/249814

Inventors:

Jordan Christopher Cookman - San Jose CA, US
Ping Dong - Cupertino CA, US
Tao Yu - Milpitas CA, US

Assignee:

CSR Technology Inc. - San Jose CA

International Classification:

H04L 27/01
H04B 3/20

US Classification:

375232, 370292

Abstract:

An adaptive known signal canceller comprising of a known signal canceller filter responsive to a known signal including a known portion of a transmitted signal, the known signal canceller filter operative to generate a filtered known signal, and a subtractor unit responsive to an input signal and operative to generate an output signal, the subtractor unit configured to subtract the filtered known signal from the input signal to generate an output signal, such that the known portion of the transmitted signal is substantially removed from the input signal. The adaptive known signal canceller further comprising of a known signal canceller update unit, responsive to a desired signal and an output signal and operative to continually adjust the coefficients of the known signal canceller filter based on the difference between the output signal and the desired signal, so that the filter coefficients substantially reflect the impulse response of a channel.

US Patent:

8150638, Apr 3, 2012

Filed:

Aug 25, 2008

Appl. No.:

12/197921

Inventors:

Shuxian Wu - San Jose CA, US
Tao Yu - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/10
G06F 17/50

US Classification:

702 57, 703 2, 716115

Abstract:

A computer-implemented method of determining parasitic capacitance for transistors within an integrated circuit can include determining a first set of coefficients for a first expression that calculates parasitic capacitance for a transistor structure according to a first plurality of parasitic capacitances derived from a plurality of two-dimensional transistor structures (). The first set of coefficients can be inserted into the first expression (). The method further can include determining a second set of coefficients for a second expression that calculates parasitic capacitance for a transistor structure according to a second plurality of parasitic capacitances derived from a plurality of three-dimensional transistor structures (). The second expression can include the first expression (). The method can include inserting the second set of coefficients into the second expression and outputting the second expression ().

US Patent:

8219872, Jul 10, 2012

Filed:

Dec 19, 2008

Appl. No.:

12/340134

Inventors:

Jordan Christopher Cookman - San Jose CA, US
Tao Yu - San Jose CA, US
Ping Dong - Cupertino CA, US
Junjie Qu - Shanghai, CN

Assignee:

CSR Technology Inc. - Sunnyvale CA

International Classification:

G06F 11/00

US Classification:

714752, 714701, 714702

Abstract:

An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by ‘b’, has a length of L+N, wherein Lis the length of the storage branch prior to appending N.

US Patent:

8359499, Jan 22, 2013

Filed:

Oct 9, 2009

Appl. No.:

12/577125

Inventors:

Sriram Mudulodu - Santa Clara CA, US
Ping Dong - Cupertino CA, US
Jordan Christopher Cookman - San Jose CA, US
Tao Yu - Milpitas CA, US

Assignee:

CSR Technology Inc. - Sunnyvale CA

International Classification:

H03M 13/00
G06F 11/00

US Classification:

714701, 714776, 714817, 375348

Abstract:

A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds to at least one of the plurality of data units deinterleaved by the data deinterleaver; and apply the deinterleaved SQI units to the corresponding deinterleaved data units.