Ted W White

US Patent:

6838322, Jan 4, 2005

Filed:

May 1, 2003

Appl. No.:

10/427577

Inventors:

Daniel T. Pham - Austin TX, US
Alexander L. Barr - Austin TX, US
Leo Mathew - Austin TX, US
Anne M. Vandooren - Austin TX, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2100
H01L 2120
H01L 213205

US Classification:

438151, 438152, 438157, 438166, 438482, 438486, 438585, 438587, 438588

Abstract:

A method for forming a polysilicon FinFET () or other thin film transistor structure includes forming an insulative layer () over a semiconductor substrate (). An amorphous silicon layer () forms over the insulative layer (). A silicon germanium seed layer () forms in association with the amorphous silicon layer () for controlling silicon grain growth. The polysilicon layer arises from annealing the amorphous silicon layer (). During the annealing step, silicon germanium seed layer (), together with silicon germanium layer (), catalyzes silicon recrystallization to promote growing larger crystalline grains, as well as fewer grain boundaries within the resulting polysilicon layer. Source (), drain (), and channel () regions are formed within the polysilicon layer. A double-gated region () forms in association with source (), drain (), and channel () to produce polysilicon FinFET ().

US Patent:

7018901, Mar 28, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/954121

Inventors:

Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Venkat R. Kolagunta - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Da Zhang - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336

US Classification:

438285, 438300, 438290

Abstract:

A semiconductor device () is formed by positioning a gate () overlying a semiconductor layer () of preferably silicon. A semiconductor material () of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel () in which a stressor material layer () is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

US Patent:

7067868, Jun 27, 2006

Filed:

Sep 29, 2004

Appl. No.:

10/952676

Inventors:

Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Venkat R. Kolagunta - Austin TX, US
Victor H. Vartanian - Dripping Springs TX, US
Da Zhang - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 27/108

US Classification:

257296, 257327

Abstract:

A semiconductor device () is formed by positioning a gate () overlying a semiconductor layer () of preferably silicon. A semiconductor material () of, for example only, SiGe or Ge, is formed adjacent the gate over the semiconductor layer and over source/drain regions. A thermal process diffuses the stressor material into the semiconductor layer. Lateral diffusion occurs to cause the formation of a strained channel () in which a stressor material layer () is immediately adjacent the strained channel. Extension implants create source and drain implants from a first portion of the stressor material layer. A second portion of the stressor material layer remains in the channel between the strained channel and the source and drain implants. A heterojunction is therefore formed in the strained channel. In another form, oxidation of the stressor material occurs rather than extension implants to form the strained channel.

US Patent:

7074664, Jul 11, 2006

Filed:

Mar 29, 2005

Appl. No.:

11/092418

Inventors:

Ted R. White - Austin TX, US
Olubunmi O. Adetutu - Austin TX, US
Robert E. Jones - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/8238

US Classification:

438199, 438692

Abstract:

A semiconductor fabrication process includes patterning a first gate electrode layer overlying a gate dielectric. A second gate electrode layer is formed overlying the first gate electrode layer and the gate dielectric. Portions of the second gate electrode layer overlying the first gate electrode layer are removed until the first and second gate electrode layers have the same thickness. A third gate electrode layer may be formed overlying the first and second gate electrode layers. The first gate electrode layer may comprise TiN and reside primarily overlying PMOS regions while the second gate electrode layer may comprise TaC or TaSiN and primarily overlie NMOS regions. Removing portions of the second gate electrode layer may include performing a chemical mechanical process (CMP) without masking the second gate electrode layer or forming a resist mask and etching exposed portions of the second gate electrode layer.

US Patent:

7160769, Jan 9, 2007

Filed:

Oct 20, 2004

Appl. No.:

10/969108

Inventors:

Ted R. White - Austin TX, US
Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Mariam G. Sadaka - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/336
H01L 29/78

US Classification:

438198, 438199, 438275, 257369, 257E21409, 257E29255

Abstract:

P channel transistors are formed in a semiconductor layer that has a (110) surface orientation for enhancing P channel transistor performance, and the N channel transistors are formed in a semiconductor layer that has a (100) surface orientation. To further provide P channel transistor performance enhancement, the direction of their channel lengths is selected based on their channel direction. The narrow width P channel transistors are preferably oriented in the direction. The wide channel width P channel transistors are preferably oriented in the direction.

US Patent:

7163903, Jan 16, 2007

Filed:

Apr 30, 2004

Appl. No.:

10/836172

Inventors:

Marius K. Orlowski - Austin TX, US
Alexander L. Barr - Crolles, FR
Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00

US Classification:

438933, 438752, 438753, 257E21, 257411, 257582, 257648

Abstract:

A semiconductor substrate having a silicon layer is provided. In one embodiment, the substrate is a silicon-on-insulator (SOI) substrate having an oxide layer underlying the silicon layer. An amorphous or polycrystalline silicon germanium layer is formed overlying the silicon layer. Alternatively, germanium is implanted into a top portion of the silicon layer to form an amorphous silicon germanium layer. The silicon germanium layer is then oxidized to convert the silicon germanium layer into a silicon dioxide layer and to convert at least a portion of the silicon layer into germanium-rich silicon. The silicon dioxide layer is then removed prior to forming transistors using the germanium-rich silicon. In one embodiment, the germanium-rich silicon is selectively formed using a patterned masking layer over the silicon layer and under the silicon germanium layer. Alternatively, isolation regions may be used to define local regions of the substrate in which the germanium-rich silicon is formed.

US Patent:

7205210, Apr 17, 2007

Filed:

Feb 17, 2004

Appl. No.:

10/780143

Inventors:

Alexander L. Barr - Crolles, FR
Dejan Jovanovic - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/30
H01L 21/46

US Classification:

438455, 257E21122

Abstract:

A first semiconductor structure has a silicon substrate, a first silicon germanium layer grown on the silicon, a second silicon germanium layer on the first silicon germanium layer, and a strained silicon layer on the second silicon germanium layer. A second semiconductor structure has a silicon substrate and an insulating top layer. The silicon layer of the first semiconductor structure is bonded to the insulator layer to form a third semiconductor structure. The second silicon germanium layer is cut to separate most of the first semiconductor structure from the third semiconductor structure. The silicon germanium layer is removed to expose the strained silicon layer where transistors are subsequently formed, which is then the only layer remaining from the first semiconductor structure. The transistors are oriented along the direction and at a 45 degree angle to the direction of the base silicon layer of the second silicon.

US Patent:

7208357, Apr 24, 2007

Filed:

Aug 17, 2004

Appl. No.:

10/919922

Inventors:

Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Crolles, FR
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/00
H01L 21/20
H01L 21/425

US Classification:

438166, 438517, 438479, 438933, 257E21285, 257E21564, 257E21703

Abstract:

A process for forming a strained semiconductor layer. The process includes implanting ions into a semiconductor layer prior to performing a condensation process on the layer. The ions assist in diffusion of atoms (e. g. germanium) in the semiconductor layer and to increase the relaxation of the semiconductor layer. After the condensation process, the layer can be used as a template layer for forming a strained semiconductor layer.