Ted C White

US Patent:

6831350, Dec 14, 2004

Filed:

Oct 2, 2003

Appl. No.:

10/677844

Inventors:

Chun-Li Liu - Mesa AZ
Alexander L. Barr - Austin TX
John M. Grant - Austin TX
Marius K. Orlowski - Austin TX
Tab A. Stephens - Austin TX
Ted R. White - Austin TX
Shawn G. Thomas - Gilbert AZ

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 2930

US Classification:

257617, 257616, 257241, 257243, 257288, 257368, 438149, 438150, 438151, 438163, 438197, 438430, 438517

Abstract:

A semiconductor structure includes a substrate comprising a first relaxed semiconductor material with a first lattice constant. A semiconductor device layer overlies the substrate, wherein the semiconductor device layer includes a second relaxed semiconductor material with a second lattice constant different from the first lattice constant. In addition, a dielectric layer is interposed between the substrate and the semiconductor device layer, wherein the dielectric layer includes a programmed transition zone disposed within the dielectric layer for transitioning between the first lattice constant and the second lattice constant. The programmed transition zone includes a plurality of layers, adjoining ones of the plurality of layers having different lattice constants with one of the adjoining ones having a first thickness exceeding a first critical thickness required to form defects and another of the adjoining ones having a second thickness not exceeding a second critical thickness. Each adjoining layer of the plurality of layers forms an interface for promoting defects in the transition zone to migrate to and terminate on an edge of the programmed transition zone. A method of making the same is also disclosed.

US Patent:

7029980, Apr 18, 2006

Filed:

Sep 25, 2003

Appl. No.:

10/670928

Inventors:

Chun-Li Liu - Mesa AZ, US
Marius K. Orlowski - Austin TX, US
Matthew W. Stoker - Mesa AZ, US
Philip J. Tobin - Austin TX, US
Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Austin TX, US
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US

Assignee:

Freescale Semiconductor Inc. - Austin TX

International Classification:

H01L 21/331

US Classification:

438311, 438479, 438404, 438459

Abstract:

A vacancy injecting process for injecting vacancies in template layer material of an SOI substrate. The template layer material has a crystalline structure that includes, in some embodiments, both germanium and silicon atoms. A strained silicon layer is then epitaxially grown on the template layer material with the beneficial effects that straining has on electron and hole mobility. The vacancy injecting process is performed to inject vacancies and germanium atoms into the crystalline structure wherein germanium atoms recombine with the vacancies. One embodiment, a nitridation process is performed to grow a nitride layer on the template layer material and consume silicon in a way that injects vacancies in the crystalline structure while also allowing germanium atoms to recombine with the vacancies. Other examples of a vacancy injecting processes include silicidation processes, oxynitridation processes, oxidation processes with a chloride bearing gas, or inert gas post bake processes subsequent to an oxidation process.

US Patent:

7056778, Jun 6, 2006

Filed:

Aug 17, 2004

Appl. No.:

10/919784

Inventors:

Chun-Li Liu - Mesa AZ, US
Mariam G. Sadaka - Austin TX, US
Alexander L. Barr - Crolles, FR
Shawn G. Thomas - Gilbert AZ, US
Ted R. White - Austin TX, US
Qianghua Xie - Chandler AZ, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H01L 21/338

US Classification:

438184, 438200

Abstract:

A process for forming strained semiconductor layers. The process include flowing a chlorine bearing gas (e. g. hydrogen chloride, chlorine, carbon tetrachloride, and trichloroethane) over the wafer while heating the wafer. In one example, the chorine bearing gas is flowed during a condensation process on a semiconductor layer that is used as a template layer for forming a strain semiconductor layer (e. g. strain silicon). In other examples, the chlorine bearing gas is flowed during a post bake of the wafer after the condensation operation.

US Patent:

20060226492, Oct 12, 2006

Filed:

Mar 30, 2005

Appl. No.:

11/094008

Inventors:

Shawn Thomas - Gilbert AZ, US
Lubomir Cergel - Geneve, CH
Mariam Sadaka - Austin TX, US
Peter Wennekers - Berlin, DE
Ted White - Austin TX, US
Andreas Wild - Grenoble, FR
Detlev Gruetzmacher - Villigen, CH
Oliver Schmidt - Stuttgart, DE

International Classification:

H01L 29/94

US Classification:

257369000

Abstract:

A semiconductor device includes a mechanically strained channel, wherein the channel comprises of a single crystalline structure of a strained semiconductor layer having a non-linear geometry, the non-linear geometry including a portion of an arch shape. The semiconductor device further includes a dielectric layer, wherein a first portion of the channel is disposed overlying a point location within the dielectric layer and a second portion of the channel is disposed overlying a portion of the dielectric layer proximate to and outside of the point location. In addition, a gate is disposed proximate to the channel for controlling current flow through the channel between first and second current handling electrodes that are coupled to the channel.