Teng Y Lin

US Patent:

7430238, Sep 30, 2008

Filed:

May 25, 2005

Appl. No.:

11/138849

Inventors:

Teng Chiang Lin - San Jose CA, US
Weimin Zeng - San Jose CA, US

Assignee:

Micronas USA, Inc. - Santa Clara CA

International Classification:

H04N 7/12

US Classification:

37524016

Abstract:

A shared pipeline architecture is provided for H. 264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.

US Patent:

20060126726, Jun 15, 2006

Filed:

May 25, 2005

Appl. No.:

11/137971

Inventors:

Teng Lin - San Jose CA, US
Hongjun Yuan - San Jose CA, US
Weimin Zeng - San Jose CA, US
Liang Peng - San Jose CA, US

International Classification:

H04N 11/04
H04N 7/12
H04N 11/02
H04B 1/66

US Classification:

375240030, 375240250, 375240230, 375240240, 375240200, 375240120

Abstract:

In one embodiment, a DSP structure includes four main sections: DEQ, IDCT for row, IDCT for column, and motion compensation. The data input sequence is organized in such a way to facilitate the data loading into hardware structures for row IDCT and column IDCT. Two types of decoding flows are enabled by the DSP structure: H.264 decoding flows (e.g., dequantization, inverse discrete Hadamard transform, intra prediction, and motion decompensation), and non-H.264 decoding flows (e.g., dequantization, row inverse discrete cosine transformation, column inverse discrete cosine transformation, and motion decompensation). The non-H.264 decoding flow can be used for standards such as MPEG1/2/4, H.263, Microsoft WMV9, and Sony Digital Video.

US Patent:

20090003451, Jan 1, 2009

Filed:

Aug 20, 2008

Appl. No.:

12/195344

Inventors:

Teng Chiang Lin - San Jose CA, US
Weimin Zeng - San Jose CA, US

Assignee:

MICRONAS USA, INC. - Santa Clara CA

International Classification:

H04N 7/26

US Classification:

37524016, 375E07124

Abstract:

A shared pipeline architecture is provided for H.264 motion vector prediction and residual decoding, and intra prediction for CABAC and CALVC entropy in Main Profile and High Profile for standard and high definition applications. All motion vector predictions and residual decoding of I-type, P-type, and B-type pictures are completed through the shared pipeline. The architecture enables better performance and uses less memory than conventional architectures. The architecture can be completely implemented in hardware as a system-on-chip or chip set using, for example, field programmable gate array (FPGA) technology or application specific integrated circuitry (ASIC) or other custom-built logic.