Teng Yang

US Patent:

20190378555, Dec 12, 2019

Filed:

Aug 26, 2019

Appl. No.:

16/550809

Inventors:

- Armonk NY, US
Xiao Sun - Pleasantville NY, US
Teng Yang - New York NY, US

International Classification:

G11C 11/22
H03K 19/177

Abstract:

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

US Patent:

20190096462, Mar 28, 2019

Filed:

Sep 27, 2017

Appl. No.:

15/717023

Inventors:

- Armonk NY, US
Xiao Sun - Pleasantville NY, US
Teng Yang - New York NY, US

International Classification:

G11C 11/22
H03K 19/177

Abstract:

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

US Patent:

20190096463, Mar 28, 2019

Filed:

Dec 31, 2017

Appl. No.:

15/859583

Inventors:

- Armonk NY, US
Xiao Sun - Pleasantville NY, US
Teng Yang - New York NY, US

International Classification:

G11C 11/22
H03K 19/177

Abstract:

Word lines intersect bit lines at a plurality of cross points where a plurality of single memory transistor synapse cells are located. Each cell includes a memory transistor; a pulse shaping unit coupled to a given one of a plurality of signal lines and a gate of the memory transistor; a logic gate having inputs coupled to a corresponding one of the word lines and a corresponding one of the bit lines, and an output coupled to the pulse shaping unit; and a pass gate arrangement. The latter is coupled to the memory transistor, the corresponding one of the word lines, the corresponding one of the bit lines, and the output of the logic gate. Pulses are applied to the gate of the memory transistor for weight adjustment during update and to interconnect the memory transistor to the corresponding one of the bit lines during inference.

US Patent:

20160358672, Dec 8, 2016

Filed:

Aug 22, 2016

Appl. No.:

15/243664

Inventors:

Mingoo Seok - New York NY, US
Peter Kinget - Summit NJ, US
Teng Yang - New York NY, US

Assignee:

The Trustees of Columbia University in the City of New York - New York NY

International Classification:

G11C 29/50
G11C 11/419

Abstract:

Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

US Patent:

20160265981, Sep 15, 2016

Filed:

Nov 3, 2014

Appl. No.:

15/033858

Inventors:

- New York NY, US
Peter R. Kinget - Summit NJ, US
Teng Yang - New York NY, US
Seongjong Kim - New York NY, US

International Classification:

G01K 7/01

Abstract:

Circuits for temperature monitoring are provided having a first voltage output and a second voltage output comprising: a first transistor having a first transistor input, a first transistor output, and a first transistor control, wherein the first transistor input is connected to a supply voltage; a first diode having a first diode input and a first diode output, wherein the first diode output is connected to ground and the first diode input is connected to the first transistor output, the first transistor control and the first voltage output; a second transistor having a second transistor input, a second transistor output, and a second transistor control, wherein the second transistor input is connected to a supply voltage; a second diode having a second diode input and a second diode output, wherein the second diode input is connected to the second transistor output, the second transistor control, and the second voltage output.

US Patent:

20160232986, Aug 11, 2016

Filed:

Feb 8, 2016

Appl. No.:

15/018834

Inventors:

Mingoo Seok - New York NY, US
Peter Kinget - Summit NJ, US
Teng Yang - New York NY, US

International Classification:

G11C 29/50

Abstract:

Circuits for estimating threshold voltages of transistors in memory device bitcells are provided. The circuits use a multiplexer, a sensor switch network, a power switch network, and an NMOS device configured as a sensor to couple a desired one the transistors in the bitcells and the NMOS device to each other, to a test voltage, and to ground. A sensor voltage node can then be measured, and based on the resulting measurement, a threshold voltage for the transistor estimate.

US Patent:

20150180521, Jun 25, 2015

Filed:

Jul 19, 2013

Appl. No.:

14/415914

Inventors:

- New York NY, US
Peter R. Kinget - Summit NJ, US
Harish Krishnaswamy - New York NY, US
Teng Yang - New York NY, US

International Classification:

H04B 1/12
H04L 25/14

Abstract:

Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.