Terrell Magee

US Patent:

8443147, May 14, 2013

Filed:

Dec 5, 2011

Appl. No.:

13/311378

Inventors:

Tony M. Brewer - Plano TX, US
Terrell Magee - Carrollton TX, US
J. Michael Andrewartha - Plano TX, US

Assignee:

Convey Computer - Richardson TX

International Classification:

G06F 12/00
G06F 13/00

US Classification:

711127, 711100, 711154, 711157

Abstract:

A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e. g. , 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e. g. , 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.

US Patent:

20100037024, Feb 11, 2010

Filed:

Aug 5, 2008

Appl. No.:

12/186344

Inventors:

Tony M. Brewer - Plano TX, US
Terrell Magee - Carrollton TX, US
J. Michael Andrewartha - Plano TX, US

Assignee:

Convey Computer - Richardson TX

International Classification:

G06F 12/08

US Classification:

711127, 711E12041

Abstract:

A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache-block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non-cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.