Terrence B Mcdaniel

US Patent:

6350679, Feb 26, 2002

Filed:

Aug 3, 1999

Appl. No.:

09/366508

Inventors:

Terrence McDaniel - Boise ID
Max F. Hineman - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438634, 438618, 438622, 438623, 438631, 438645, 438647, 438648

Abstract:

The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.

US Patent:

6844255, Jan 18, 2005

Filed:

Oct 9, 2001

Appl. No.:

10/011212

Inventors:

Terrence McDaniel - Boise ID, US
Max F. Hineman - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 214763

US Classification:

438618, 438622, 438623, 438631, 438634, 438645, 438647, 438648

Abstract:

The invention comprises methods of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry. In one implementation, a method of providing an interlevel dielectric layer intermediate different elevation conductive metal layers in the fabrication of integrated circuitry includes forming a conductive metal interconnect layer over a substrate. An insulating dielectric mass is provided about the conductive metal interconnect layer. The insulating dielectric mass has a first dielectric constant. At least a majority of the insulating dielectric mass is etched away from the substrate. After the etching, an interlevel dielectric layer is deposited to replace at least some of the etched insulating dielectric material. The interlevel dielectric layer has a second dielectric constant which is less than the first dielectric constant.

US Patent:

7118966, Oct 10, 2006

Filed:

Aug 23, 2004

Appl. No.:

10/925158

Inventors:

Scott A. Southwick - Boise ID, US
Alex J. Schrinsky - Boise ID, US
Terrence B. McDaniel - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

438259, 438429, 438430

Abstract:

This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line. In one implementation, a conductive contact is formed adjacent to and insulated from the conductive line.

US Patent:

7329618, Feb 12, 2008

Filed:

Jun 28, 2005

Appl. No.:

11/168893

Inventors:

Randall Culver - Boise ID, US
Terrence B. McDaniel - Boise ID, US
Hongmei Wang - Centreville VA, US
James L. Dale - Woodbridge VA, US
Richard H. Lane - Boise ID, US
Fred D. Fishburn - Woodbridge VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/31
H01L 21/265
H01L 21/266

US Classification:

438780, 438514, 438778, 257E21026, 257E21618

Abstract:

An ion implanting method includes forming a pair of spaced and adjacent features projecting outwardly from a substrate. At least outermost portions of the pair of spaced features are laterally pulled away from one another with a patterned photoresist layer received over the features and which has an opening therein received intermediate the pair of spaced features. While such spaced features are laterally pulled, a species is ion implanted into substrate material which is received lower than the pair of spaced features. After the ion implanting, the patterned photoresist layer is removed from the substrate. Other aspects and implementations are contemplated.

US Patent:

7341909, Mar 11, 2008

Filed:

Apr 6, 2005

Appl. No.:

11/099972

Inventors:

Terrence B. McDaniel - Boise ID, US
Scott A. Southwick - Boise ID, US
Fred D. Fishburn - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/8242
H01L 21/4763

US Classification:

438253, 438239, 438618, 438625, 257E21646, 257E23169

Abstract:

The invention includes methods of forming semiconductor constructions in which electrically conductive structures are formed between bitlines to electrically connect with storage node contacts. The bitlines can be formed within trenches having faceted top portions. The invention also includes semiconductor structures containing trenches with faceted top portions, and containing bitlines within the trenches.

US Patent:

7364966, Apr 29, 2008

Filed:

Aug 22, 2005

Appl. No.:

11/208972

Inventors:

James E. Green - Nampa ID, US
Terrence B. McDaniel - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/8242

US Classification:

438253, 438396, 257E21646

Abstract:

A method for use during fabrication of a semiconductor device comprises the formation of buried digit lines and contacts. During formation, a buried bit line layer may be used as a mask to etch one or more openings in a dielectric layer. A conductive layer is then formed in the one or more openings in the dielectric layer, and is then planarized to form one or more individual contact plugs. Next, the buried bit line layer is etched to recess the buried bit line layer, and a capacitor plate is formed to contact the contact plug.

US Patent:

7445996, Nov 4, 2008

Filed:

Mar 8, 2005

Appl. No.:

11/074563

Inventors:

Terrence McDaniel - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

438258, 438682

Abstract:

A process and apparatus directed to forming low resistance contacts in both the memory cell array and peripheral logic circuitry areas of a semiconductor device, for example, a DRAM memory device, is disclosed. In a buried bit line connection process flow, the present invention utilizes chemical vapor deposition of titanium to form titanium silicide in contact structures of the peripheral logic circuitry areas and physical vapor deposition to provide a metal mode (metallic) titanium layer in contact with the poly plugs in the memory cell array area of a semiconductor device, for example, a DRAM memory device according to the present invention. In this manner, the present invention avoids the potential drawbacks such as voiding in the poly plugs of the memory cell array due to the present of titanium silicide, which can cause significant reduction of device drain current and in extreme cases cause electrical discontinuity.

US Patent:

7491641, Feb 17, 2009

Filed:

Apr 27, 2006

Appl. No.:

11/412524

Inventors:

Scott A. Southwick - Boise ID, US
Alex J. Schrinsky - Boise ID, US
Terrence B. McDaniel - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/4763

US Classification:

438639, 438259, 438429, 438430, 438642, 438648

Abstract:

This invention includes methods of forming conductive lines, and methods of forming conductive contacts adjacent conductive lines. In one implementation, a method of forming a conductive line includes forming a conductive line within an elongated trench within first insulative material over a semiconductive substrate. The conductive line is laterally spaced from opposing first insulative material sidewall surfaces of the trench. The conductive line includes a second conductive material received over a different first conductive material. The second conductive material is recessed relative to an elevationally outer surface of the first insulative material proximate the trench. A second insulative material different from the first insulative material is formed within the trench over a top surface of the conductive line and within laterally opposing spaces received between the first insulative material and the conductive line. In one implementation, a conductive contact is formed adjacent to and insulated from the conductive line.