Terry J Lee

US Patent:

6820181, Nov 16, 2004

Filed:

Aug 29, 2002

Appl. No.:

10/232473

Inventors:

Joseph M. Jeddeloh - Shoreview MN
Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1200

US Classification:

711169, 710 52

Abstract:

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

US Patent:

7107415, Sep 12, 2006

Filed:

Jun 20, 2003

Appl. No.:

10/601253

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry R. Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 13/00
G06F 3/00

US Classification:

711154, 711158, 711168, 711170, 711105, 710 52, 710 36

Abstract:

A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

US Patent:

7249236, Jul 24, 2007

Filed:

Oct 12, 2004

Appl. No.:

10/963824

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry R. Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 12/00

US Classification:

711169, 710 52

Abstract:

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.

US Patent:

7366920, Apr 29, 2008

Filed:

Jun 20, 2003

Appl. No.:

10/601222

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32
G06F 11/30

US Classification:

713300, 713320, 713323, 713324, 713330, 713340

Abstract:

A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

US Patent:

7428644, Sep 23, 2008

Filed:

Jun 20, 2003

Appl. No.:

10/601222

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32
G06F 11/30

US Classification:

713300, 713320, 713323, 713324, 713330, 713340

Abstract:

A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

US Patent:

7437579, Oct 14, 2008

Filed:

May 11, 2006

Appl. No.:

11/433218

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1/00
G06F 1/26
G06F 1/32
G06F 11/30

US Classification:

713300, 713320, 713323, 713324, 713330, 713340

Abstract:

A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by tracking system usage, manifested by read and write commands issued to the memory module, or by measuring temperature changes indicating a level of device activity beyond normal refresh activity. Alternatively, measured activity levels can be transmitted over a system bus to a centralized power management controller which, responsive to the activity level packets transmitted by remote memory modules, direct devices of those remote memory modules to a reduced power state. The centralized power management controller could be disposed on a master memory module or in a memory or system controller.

US Patent:

7529896, May 5, 2009

Filed:

May 11, 2006

Appl. No.:

11/433201

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry R. Lee - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 13/00
G06F 3/00

US Classification:

711154, 711158, 711168, 711170, 711105, 710 52, 710 36

Abstract:

A memory module includes a memory hub coupled to several memory devices. The memory hub includes a posted write buffer that stores write requests so that subsequently issued read requests can first be coupled to the memory devices. The write request addresses are also posted in the buffer and compared to subsequent read request addresses. In the event of a positive comparison indicating that a read request is directed to an address to which an earlier write request was directed, the read data are provided from the buffer. When the memory devices are not busy servicing read request, the write requests can be transferred from the posted write buffer to the memory devices. The write requests may also be accumulated in the posted write buffer until either a predetermined number of write requests have been accumulated or the write requests have been posted for a predetermined duration.

US Patent:

7716444, May 11, 2010

Filed:

Jul 24, 2007

Appl. No.:

11/881010

Inventors:

Joseph M. Jeddeloh - Shoreview MN, US
Terry R. Lee - Boise ID, US

Assignee:

Round Rock Research, LLC - Mount Kisco NY

International Classification:

G06F 12/00

US Classification:

711169

Abstract:

A computer system includes a memory hub controller coupled to a plurality of memory modules. The memory hub controller includes a memory request queue that couples memory requests and corresponding request identifier to the memory modules. Each of the memory modules accesses memory devices based on the memory requests and generates response status signals from the request identifier when the corresponding memory request is serviced. These response status signals are coupled from the memory modules to the memory hub controller along with or separate from any read data. The memory hub controller uses the response status signal to control the coupling of memory requests to the memory modules and thereby control the number of outstanding memory requests in each of the memory modules.