Terry J Lee

US Patent:

6356106, Mar 12, 2002

Filed:

Sep 12, 2000

Appl. No.:

09/659334

Inventors:

Roy Greeff - Boise ID
Terry R. Lee - Boise ID
Ron Harrison - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03K 190175

US Classification:

326 30, 326 86, 326 90, 710101, 710126, 333 22 R, 333 32, 333 173

Abstract:

An active termination circuit is incorporated into the devices connected to a multidrop bus. By including the active termination circuit on the devices instead of the bus, termination resistors can be removed from the system PCB, which saves costs and frees up precious space on the PCB. The active termination circuit has a termination enabled state and a termination disabled state. The active termination circuit is selectively placed into the enabled or disabled states in specified devices depending upon, for example, device location or communication traffic on the bus. The multidrop system can also utilize a separate passive termination mechanism in combination with the active termination circuits utilized in the devices.

US Patent:

6368136, Apr 9, 2002

Filed:

Apr 6, 2001

Appl. No.:

09/827707

Inventors:

David J. Corisis - Meridian ID
Jerry M. Brooks - Caldwell ID
Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01R 1362

US Classification:

439330, 439 70

Abstract:

A semiconductor package for vertically surface mounting to a printed circuit board having retention apparatus for holding the package thereto.

US Patent:

6374360, Apr 16, 2002

Filed:

Dec 11, 1998

Appl. No.:

09/209587

Inventors:

Brent Keeth - Boise ID
Terry R. Lee - Boise ID
Kevin Ryan - Eagle ID
Troy A. Manning - Meridian ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 112

US Classification:

713400

Abstract:

A synchronization circuit performs bit-to-bit timing correction of respective digital signals in digital signal packets applied to a packetized memory device. Each digital signal packet includes a plurality of digital signals applied to respective latches. A clock generator circuit generates a plurality of internal clock signals responsive to the external clock signal, each internal clock signal having a corresponding phase relative to the external clock signal. A plurality of selection circuits applies respective internal clock signals to respective latches in response to a phase command signal. An evaluation circuit receives digital signals sequentially stored in a selected one of the latches and generates a results signal indicating whether each of the digital signals has an expected value. A control circuit sequentially selects the latches and operates for each selected latch to adjust the phase command signals applied to the selection circuit coupled to the selected latch and store respective results signals sequentially received from the evaluation circuit for each phase command signal. The control circuit generates a final phase command signal from the stored results signals and applies each final phase command signal to the corresponding selection circuit.

US Patent:

6392948, May 21, 2002

Filed:

Aug 29, 1996

Appl. No.:

08/705149

Inventors:

Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365222, 365201

Abstract:

A semiconductor device (such as a DRAM) includes a memory array that has dynamic memory cells. In a self refresh test mode, a self refresh test mode controller monitors and/or controls various blocks and internal signals in semiconductor device. The self refresh test mode controller may communicate with a remote testing device through various conductors including one or more DQ lines and/or one or more address lines. The self refresh test mode controller provides at least one or more of the following four functions: (1) the ability to control internal signals while in self refresh test mode; (2) the ability to monitor internal signals while in self refresh test mode; (3) the ability to put in a programmable delay, change the delay, or change internal timing while in self refresh test mode (add delay or make delay programmable, adjustable); (4) the ability to have the device do a device read in a self refresh test mode (the DQ pins may be used to read particular data on the row, while the column address is frozen). As examples, the following signals may be analyzed and acted upon by the self refresh test mode controller, or transmitted through the self refresh test mode controller to a remote testing device: (1) internal {overscore (RAS)} signals; (2) bits from refresh counter; (3) {overscore (RAS)} chain; and (4) equilibrate signals. As examples, the following are signals that may be received or produced by the self refresh test mode controller, and then analyzed and acted upon or transmitted through the self refresh test mode controller to one or more of the various blocks of the semiconductor device: (1) a signal overriding internal {overscore (RAS)} signals generated by self refresh circuitry (including initiating a row change or the rate at which row change occurs); (2) a signal that causes control of incrementing a refresh counter; (3) signals that alter internal time or programmable delay elements.

US Patent:

6398573, Jun 4, 2002

Filed:

Jul 20, 2001

Appl. No.:

09/910318

Inventors:

David J. Corisis - Meridian ID
Jerry M. Brooks - Caldwell ID
Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01R 1362

US Classification:

439330, 439 70, 439326

Abstract:

A semiconductor package for vertically surface mounting to a printed circuit board having retention apparatus for holding the package thereto.

US Patent:

6415340, Jul 2, 2002

Filed:

Sep 15, 2000

Appl. No.:

09/663035

Inventors:

Kevin J. Ryan - Eagle ID
Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1312

US Classification:

710 52, 710130, 710 29, 710 61, 710 60, 710 25, 710 38, 710 36, 710 58, 711167, 711152

Abstract:

A synchronous dynamic random access memory (âSDRAMâ) operates with matching read and write latencies. To prevent data collision at the memory array, the SDRAM includes interim address and interim data registers that temporarily store write addresses and input data until an available interval is detected where no read data or read addresses occupy the memory array. During the available interval, data is transferred from the interim data register to a location in the memory array identified by the address in the interim array register. In one embodiment, the SDRAM also includes address and compare logic to prevent reading incorrect data from an address to which the proper data has not yet been written. In another embodiment, a system controller monitors commands and addresses and inserts no operation commands to prevent such collision of data and addresses.

US Patent:

6442644, Aug 27, 2002

Filed:

Aug 10, 1998

Appl. No.:

09/132158

Inventors:

David B. Gustavson - Los Altos CA
David V. James - Palo Alto CA
Hans A. Wiggers - Saratoga CA
Peter B. Gillingham - Kanata, CA
Cormac M. OConnell - Kanata, CA
Bruce Millar - Stittsville, CA
Jean Crepeau - Nepean, CA
Kevin J. Ryan - Eagle ID
Terry R. Lee - Boise ID
Brent Keeth - Boise ID
Troy A. Manning - Meridian ID
Donald N. North - Saratoga CA
Desi Rhoden - Phoenix AZ
Henry Stracovsky - San Jose CA
Yoshikazu Morooka - Hyogo, JP

Assignee:

Advanced Memory International, Inc. - San Jose CA

International Classification:

G06F 1200

US Classification:

711105, 365194

Abstract:

A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

US Patent:

6455351, Sep 24, 2002

Filed:

Mar 27, 2001

Appl. No.:

09/819297

Inventors:

Larry D. Kinsman - Boise ID
Jerry M. Brooks - Caldwell ID
Warren M. Farnworth - Nampa ID
Walter L. Moden - Meridian ID
Terry R. Lee - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2144

US Classification:

438107, 257727

Abstract:

A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferable, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.