Terry M O'Brien

US Patent:

50288091, Jul 2, 1991

Filed:

Mar 7, 1989

Appl. No.:

7/320137

Inventors:

Tak Watanabe - Los Altos CA
John J. Youden - Cupertino CA
Terry P. O'Brien - Cupertino CA
Donald A. Telian - Roseville CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

H01H 150

US Classification:

307137

Abstract:

A computer bus structure is provided which permits replacement of removable modules during operation of a computer wherein means are provided to precharge signal output lines to within a predetermined range prior to the usage of the signal output lines to carry signals, and further, wherein means are provided to minimize arcing to pins designed to carry the power and signals of a connector. In a specific embodiment, pin length, i. e. , separation between male and female components of the connector, are subdivided into long pin length and short pin length. Ground connections and power connections for each voltage level are assigned to the long pin lengths. Signal connections and a second power connection for each voltage level is assigned to the short pin lengths. The precharge/prebias circuit comprises a resistor divider coupled between a power source and ground with a high impedance tap coupled to a designated signal pin, across which is coupled a charging capacitor or equivalent representing the capacitance of the signal line. Bias is applied to the precharge/prebias circuit for a sufficient length of time to precharge the signal line to a desired neutral signal level between expected high and low signal values prior to connection of the short pin to its mate.