Terry L Sterrett from 21101 Shaw Ln, Huntington Beach, CA 92646, age 69, Phone: 7144754954

Resumes

Terry Sterrett

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Location:

Detroit, MI

Industry:

Medical Devices

Work:

St. Jude Medical 2010 - 2015
Principal Engineer
Henkel Electronic Materials Llc 2007 - 2010
Engineering Scientist
Medtronic 2003 - 2007
Senior Principal Engineer
Intel Corporation 2000 - 2003
Senior Engineer

Skills:

Process Engineering
Process Development
Design Assurance
Reliability Engineering
Reliability Test
Failure Analysis
Root Cause Analysis
Physics of Failure
Design For Manufacturing
Qfd
Dfss
Design Control
Minitab
Jmp
Spc
Supplier Development
Supplier Quality
Medical Devices
Iso 13485
21Cfr820
Iso 14971
Test Method Development
Test Method Validation
Fmea
Plastic Extrusion
Injection Molding
Materials Characterization
Microelectronics Assembly
Design of Experiments
Capa
Certified Black Belt
Shape Memory Alloys
Project Management
Cross Functional Team Leadership
Statistics Mentorship
R&D
Product Development
Invention
Forensic Engineering
Expert Witness
Research and Development

Terry Sterrett

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Us Patents

Integrated Circuit Device With Covalently Bonded Connection Structure
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US Patent:

6586843, Jul 1, 2003
Filed:

Nov 8, 2001
Appl. No.:

09/986409
Inventors:

Terry Sterrett - Cave Creek AZ
Tim Chen - Chandler AZ
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2348
US Classification:

257778, 257734, 257737, 174257, 174260
Abstract:

A method and apparatus provides increased operative life for flip-chip devices that are produced from an integrated circuit formed with electrically conductive bumps bonded to a printed circuit board substrate. The bumps and the substrate are formed from similar materials that allow control of the degree of latency for each element and produce a covalently bonded laminate structure when the bumps and substrate are brought together. The covalently bonded structure decreases bump fatigue to lengthen the operative life of the flip-chip device.

Surface Treatment For Microelectronic Device Substrate
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US Patent:

6794225, Sep 21, 2004
Filed:

Dec 20, 2002
Appl. No.:

10/327645
Inventors:

Rahul Manepalli - Phoenix AZ
Terry Sterrett - Cave Creek AZ
Vassoudevane Lebonheur - Tempe AZ
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 2148
US Classification:

438127
Abstract:

Embodiments of the methods of the present invention provide a Molded Matrix Array Package (MMAP) carrier substrate panel that prevents underfill wetting in the inter-die areas. Surface treatments are provided via plasmas and/or patterned chemical depositions that reduce the surface free energy of the inter-die area to below the surface free energy of the underfill material. The surface treatments prevent the underfill material from wetting the carrier substrate panel and therefore encroachment upon the inter-die area. This provides a underfill material-free inter-die area allowing adhesion between the mold compound and carrier substrate.

Method And Apparatus For Improving An Integrated Circuit Device
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US Patent:

7000821, Feb 21, 2006
Filed:

Jul 1, 2003
Appl. No.:

10/612804
Inventors:

Terry Sterrett - Cave Creek AZ, US
Tim Chen - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

B23K 31/02
US Classification:

22818022, 228246
Abstract:

A method and apparatus provides increased operative life for flip-chip devices that are produced from an integrated circuit formed with electrically conductive bumps bonded to a printed circuit board substrate. The bumps and the substrate are formed from similar materials that allow control of the degree of latency for each element and produce a covalently bonded laminate structure when the bumps and substrate are brought together. The covalently bonded structure decreases bump fatigue to lengthen the operative life of the flip-chip device.

Wafer-Level Underfill Process Making Use Of Sacrificial Contact Pad Protective Material
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US Patent:

7059048, Jun 13, 2006
Filed:

Jun 7, 2002
Appl. No.:

10/165551
Inventors:

Paul Koning - Chandler AZ, US
Terry Sterrett - Cave Creek AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01K 3/10
US Classification:

29852, 29846, 29830, 29843, 29739, 29740, 29840, 174 524, 361760, 439 66, 439 68, 439 72, 439 74, 439 75
Abstract:

A method for connecting electronic components, such as, an integrated circuit die and a package substrate, is described. According to one aspect of the invention, a contact pad protective material is applied on one or more of the contact pads on an integrated circuit die. The underfill material is applied to the surface of the die not covered by the contact pad protective material and the underfill material is partially cured in a curing oven. The contact pad material is removed leaving openings over the respective surface of the contact pad. A one or more contacts on a package substrate is inserted into the openings, electronically connecting the contacts to the contact pads.

Methods And Devices For Supporting Substrates Using Fluids
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US Patent:

7144299, Dec 5, 2006
Filed:

May 9, 2005
Appl. No.:

11/125605
Inventors:

Leonel R. Arana - Phoenix AZ, US
Terry L. Sterrett - Cave Creek AZ, US
Devendra Natekar - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

B24B 1/00
US Classification:

451 28, 451 54, 451364, 269 7, 29559
Abstract:

Electronic device support and processing methods are described. One embodiment includes a method of processing an electronic device including solder bumps extending therefrom. The method includes providing at least one fluid selected from the group consisting of electrorheological fluids and magnorheological fluids on a support structure. The solder bumps extending from the electronic device are positioned in the fluid. The fluid is activated by applying a field selected from the group consisting of an electric field and a magnetic field to the fluid. The activated fluid mechanically holds the electronic device in place. A surface of the electronic device is polished while the electronic device is held in place by the activated fluid. The fluid is deactivated by removing the applied field from the fluid, and the electronic device is separated from the deactivated fluid. Other embodiments are described and claimed.

Stackable Integrated Circuit Packaging
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US Patent:

7345361, Mar 18, 2008
Filed:

Dec 4, 2003
Appl. No.:

10/728324
Inventors:

Debendra Mallik - Chandler AZ, US
Kinya Ichikawa - Tsukuba, JP
Terry L. Sterrett - Cave Creek AZ, US
Johanna Swan - Scottsdale AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 23/02
US Classification:

257686, 257777, 2281801
Abstract:

A system may include an integrated circuit die, an integrated circuit package coupled to the integrated circuit die, mold compound in contact with the integrated circuit die and the integrated circuit package, and an interconnect coupled to the integrated circuit package. A first portion of the interconnect may be in contact with the mold compound, a second portion of the interconnect might not contact the mold compound, and a third portion of the interconnect may be in contact with the integrated circuit package.

Interconnection Designs And Materials Having Improved Strength And Fatigue Life
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US Patent:

7387827, Jun 17, 2008
Filed:

Apr 30, 2003
Appl. No.:

10/427168
Inventors:

Terry Lee Sterrett - Cave Creek AZ, US
Richard J. Harries - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

B32B 3/10
H01L 23/48
US Classification:

428131, 428137, 428138, 257690, 257703
Abstract:

Methods and designs for increasing interconnect areas for interconnect bumps are disclosed. An interconnect bump may be formed on a substrate such that the interconnect bump extends beyond a contact pad onto a substrate. An interconnect bump may be formed on a larger contact pad, the bump having a large diameter.

Etched Interposer For Integrated Circuit Devices
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US Patent:

7413995, Aug 19, 2008
Filed:

Aug 23, 2004
Appl. No.:

10/924396
Inventors:

Terry L. Sterrett - Cave Creek AZ, US
Devendra Natekar - Chandler AZ, US
Assignee:

Intel Corporation - Santa Clara CA
International Classification:

H01L 21/44
H01L 21/48
US Classification:

438734, 438112, 438118, 438701, 438708, 257E21219
Abstract:

In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are mechanically and electrically connected using an interposer. In one embodiment, the interposer includes columnar interconnects which may be fabricated by etching a conductive member such as copper foil, for example. In one application, the pitch or center to center spacing of the columnar interconnects may be defined by masking techniques to provide an interconnect pitch suitable for a particular application. In yet another aspect, etching rates may be controlled to provide height to width aspect ratios of the columnar interconnects which are suitable for various applications.