Thanh Q Truong

US Patent:

20070098924, May 3, 2007

Filed:

Oct 27, 2005

Appl. No.:

11/260704

Inventors:

Thanh Truong - Garden Grove CA, US

International Classification:

A41G 1/00
A01N 3/00
A01N 1/00
A01G 5/06

US Classification:

428017000, 428018000, 427004000

Abstract:

An embodiment of the present invention is a technique to create plant model with realism. A tree core having a trunk and branches is created. The tree core is pre-coated with a clear oil-based liquid. A coat is formed to cover the tree core with a composite mixture. The composite mixture contains at least a paint component, a color pigment, a binder component, and a glue component.

US Patent:

52710700, Dec 14, 1993

Filed:

Nov 6, 1992

Appl. No.:

7/972403

Inventors:

Thanh D. Truong - Walnut CA
Vinod Kadakia - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06K 936

US Classification:

382 50

Abstract:

A circuit for increasing the speed of conversion of image pixels from one number of bits to another by processing a plurality of pixels in parallel. The conversion of each pixel typically results in a new value and an error term which is divided up among adjacent pixels. By using a plurality of separate conversion circuits, one for each line, and by processing the xth pixel on one line in parallel with the x-2 pixel on the next line, the plurality of pixels can be processed in parallel. All circuits are identical except that the first circuit must get the error term of the line above it from memory, and the last of the parallel circuits must store in memory the error term for the next plurality of lines.

US Patent:

60786965, Jun 20, 2000

Filed:

Jun 29, 1998

Appl. No.:

9/106734

Inventors:

Uoc H. Nguyen - Long Beach CA
Kien T. Nguyen - Torrance CA
Abraham E. Claproth - Culver City CA
Thanh D. Truong - Walnut CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06K 936
G06K 938
G06K 946

US Classification:

382253

Abstract:

Printing hints can be efficiently compressed in a system using hierarchical compression (HVQ) by first using HVQ to generate compressed codewords, and then adding the printing hint to the codewords to generate an intermediate form of codeword, before sending this intermediate form to a pattern matching lossless compressor for final compression. Even though the same printing hint may be applied to a number of codewords, the overall compression will be affected very little by the addition of the printing hints since the hints are identical over a large number of codewords in series.

US Patent:

56548060, Aug 5, 1997

Filed:

May 6, 1996

Appl. No.:

8/642991

Inventors:

Thanh D. Truong - Walnut CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H04N 141

US Classification:

358427

Abstract:

A circuit for decoding one non-zero JPEG encoded pixel per clock cycle, the coded word being of variable length. For a pixel with leading zeros, a two stage pipeline is used, the first stage having one adder for calculating an delta value between the smallest number the variable length portion could be and the actual value, the second stage being an adder for adding the delta value to a base address to generate an address for a look up table, the output being the decoded value. This takes two clock periods to decode a pixel having at least one leading zero. For the Huffman code portion of encoded pixels with no leading zero's, only ten versions of which exist, a gate array for each is provided. Each detects one version and outputs the decoded Huffman code data in one clock cycle. A multiplexer then either selects the decoded data with no leading zero's in one clock cycle or the data with at least one leading zero in two clock cycles.

US Patent:

57933782, Aug 11, 1998

Filed:

Mar 22, 1996

Appl. No.:

8/620186

Inventors:

Thanh D. Truong - Walnut CA
Vinod Kadakia - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

G06T 300

US Classification:

345437

Abstract:

A circuit for rotating a digital image through any angle at the rate of one pixel per clock period. First, the circuit divides the image to be rotated into blocks which can be rotated without pause once each is started. Then a nearest neighbor calculating circuit is used to determine the value of each rotated pixel in the block. The circuit is divided and pipelined so that each part can produce its output in one clock cycle. The nearest neighbor calculation is done in two sections of the circuit, and other sections of the circuit set up initial conditions or provide for transitions from one rotated scan line, or block, to the next.

US Patent:

56869150, Nov 11, 1997

Filed:

Dec 27, 1995

Appl. No.:

8/579113

Inventors:

Frank M. Nelson - Sherman Oaks CA
Thanh D. Truong - Walnut CA
Vinod Kadakia - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H03M 740

US Classification:

341 65

Abstract:

A method of decoding Huffman-encoded words at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for odd numbered code and one for even numbered code, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word per clock cycle.

US Patent:

56525826, Jul 29, 1997

Filed:

Dec 29, 1995

Appl. No.:

8/581687

Inventors:

Thanh D. Truong - Walnut CA
Vinod Kadakia - Rancho Palos Verdes CA

Assignee:

Xerox Corporation - Stamford CT

International Classification:

H03M 740

US Classification:

341 65

Abstract:

A circuit for decoding Huffman-encoded words describing color pixels in the Lab color space at the rate of one per clock cycle. The encoded words are formed into two strings of bits, one for coded L words and one for a and b words, each set of a and b words encoded into one Huffman code word, and two decoders in parallel are used, each first shifting in a number of coded bits during a first clock period, and converting the Huffman code to data on a second clock period. The two parallel decoders are timed so that the shift cycle of one decoder occurs at the same time as the conversion cycle of the other. Finally, the two streams of decoded data words are combined into one stream. The result is one output data word, either L or ab, per clock cycle.