Theodore D Robinson

US Patent:

50161679, May 14, 1991

Filed:

Dec 21, 1987

Appl. No.:

7/135845

Inventors:

Kham X. Nguyen - Milpitas CA
Theodore S. Robinson - Cupertino CA
Michael D. Taylor - San Jose CA
Kevin L. Daberkow - San Jose CA

Assignee:

Amdahl Corporation - Sunnyvale CA

International Classification:

G06F 1314
G06F 1516

US Classification:

364200

Abstract:

In a multiprocessor system with an interleaved memory, predicted busy terms for interleaves of the main store being accessed are sent to each processor in the system, so that they will not waste pipe flows making requests to the busy interleaves. The predicted busy term is lowered before access to the interleaves is complete, to allow for the latency between the time the processor sets up the request and the time the main store system receives it. Contention occurs when several processors request access to the same interleave of main store. To detect deadlocks, a counter for each processor keeps track of the number of consecutive requests from that processor which have been rejected. Once the number reaches a threshold for a first processor, its counter initiates a state machine which inhibits other processors from making requests to the main store until the first processor is successful in gaining access.