Theodore J Yoder

US Patent:

20210125094, Apr 29, 2021

Filed:

Oct 23, 2019

Appl. No.:

16/661434

Inventors:

- Armonk NY, US
Theodore James Yoder - White Plains NY, US
Andrew W. Cross - Yorktown Heights NY, US
Guanyu Zhu - Ossining NY, US

International Classification:

G06N 10/00
G06F 17/16
G06F 16/901

Abstract:

Techniques regarding encoding a quantum circuit to a trivalent lattice scheme to identify flag qubit outcomes are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise a graph component that can encode a quantum circuit to a trivalent lattice that maps an ancilla qubit to a plurality of data qubits via a plurality of flag qubits based on a connectivity scheme of the quantum circuit.

US Patent:

20210019223, Jan 21, 2021

Filed:

Jul 15, 2019

Appl. No.:

16/512143

Inventors:

- ARMONK NY, US
Guanyu Zhu - YORKTOWN HEIGHTS NY, US
Theodore James Yoder - White Plains NY, US
Andrew W. Cross - Yorktown Heights NY, US

International Classification:

G06F 11/10
G06N 10/00

Abstract:

A method of error correction for a quantum computer includes identifying each of a plurality of physical qubits arranged in a lattice pattern over a surface in a quantum processor of the quantum computer as a one of a data qubit, an ancilla qubit or a flag qubit to define a plurality of data qubits, ancilla qubits and flag qubits. Each pair of interacting data qubits interact with a flag qubit and adjacent flag qubits both interact with a common ancilla qubit. The method further includes performing measurements of weight-four stabilizers, weight-two stabilizers, or both of a surface code formed using at least a sub-plurality of the plurality of physical qubits, or performing measurements of weight-four Bacon-Shor type gauge operators; and correcting fault-tolerantly quantum errors in one or more of the at least sub-plurality of physical qubits based on a measurement from at least one flag qubit.

US Patent:

20200341837, Oct 29, 2020

Filed:

Aug 15, 2019

Appl. No.:

16/542094

Inventors:

- Armonk NY, US
Christopher Chamberland - Southbury CT, US
Jay M. Gambetta - Yorktown Heights NY, US
Jared B. Hertzberg - Yorktown Heights NY, US
Theodore J. Yoder - White Plains NY, US
Guanyu Zhu - Yorktown Heights NY, US

International Classification:

G06F 11/10
G06N 10/00

Abstract:

A quantum computer includes a quantum processor that includes a first plurality of qubits arranged in a hexagonal lattice pattern such that each is substantially located at a hexagon apex, and a second plurality of qubits each arranged substantially along a hexagon edge. Each of the first plurality of qubits is coupled to three nearest-neighbor qubits of the second plurality of qubits, and each of the second plurality of qubits is coupled to two nearest-neighbor qubits of the first plurality of qubits. Each of the second plurality of qubits is a control qubit at a control frequency. Each of the first plurality of qubits is a target qubit at one of a first target frequency or a second target frequency. The quantum computer includes an error correction device configured to operate on the hexagonal lattice pattern of the plurality of qubits so as to detect and correct data errors.