Thomas J Adam

US Patent:

7037798, May 2, 2006

Filed:

Nov 12, 2004

Appl. No.:

10/904482

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Kevin K. Chan - Staten Island NY, US
Alvin J. Joseph - Williston VT, US
Marwan H. Khater - Poughkeepsie NY, US
Qizhi Liu - Essex Junction VT, US
Beth Ann Rainey - Williston VT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/331

US Classification:

438312, 438316, 438318, 438320, 438341, 438350, 438356, 438357, 438359

Abstract:

The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e. g. , high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

US Patent:

7119416, Oct 10, 2006

Filed:

Jun 29, 2005

Appl. No.:

11/169444

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Kevin K. Chan - Staten Island NY, US
Alvin J. Joseph - Williston VT, US
Marwan H. Khater - Poughkeepsie NY, US
Qizhi Liu - Essex Junction VT, US
Beth Ann Rainey - Williston VT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/82
H01L 29/70

US Classification:

257592, 257E21044

Abstract:

The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e. g. , high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

US Patent:

7129129, Oct 31, 2006

Filed:

Mar 29, 2004

Appl. No.:

10/708861

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
David C. Ahlgren - Wappingers Falls NY, US
Kangguo Cheng - Beacon NY, US
Ramachandra Divakaruni - Ossining NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00

US Classification:

438242, 438244, 438396, 438931

Abstract:

A method of forming a trench in a semiconductor substrate includes a step of converting the cross section of the upper portion of the trench from octagonal to rectangular, so that sensitivity to alignment errors between the trench lithography and the active area lithography is reduced. Applications include a vertical transistor that becomes insensitive to misalignment between the trench and the litho for the active area, in particular a DRAM cell with a vertical transistor.

US Patent:

7172930, Feb 6, 2007

Filed:

Jul 2, 2004

Appl. No.:

10/883887

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Joel P. de Souza - Putnam Valley NY, US
Keith E. Fogel - Mohegan Lake NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Ghavam Shahidi - Pound Ridge NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/84
H01L 21/331
H01L 21/8222
H01L 21/36

US Classification:

438150, 438311, 438409, 438413, 438479, 438481, 438967, 257E21562, 257E21563, 257E21565

Abstract:

A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

US Patent:

7342293, Mar 11, 2008

Filed:

Dec 5, 2005

Appl. No.:

11/164757

Inventors:

Thomas A. Wallner - Pleasant Valley NY, US
Thomas N. Adam - Poughkeepsie NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Joel P. De Souza - Putnam Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/082
H01L 27/102
H01L 29/70
H01L 31/11
H01L 29/00

US Classification:

257565, 257374, 257446, 257511, 257512, 257525, 257526, 257527, 257555, 257556, 257557, 257558, 257564, 257592

Abstract:

The present invention relates to bipolar junction transistors (BJTS). The collector region of each BJT is located in a semiconductor substrate surface and adjacent to a first shallow trench isolation (STI) region. A second STI region is provided, which extends between the first STI region and the collection region and undercuts a portion of the active base region with an undercut angle of not more than about 90. For example, the second STI region may a substantially triangular cross-section with an undercut angle of less than about 90, or a substantially rectangular cross-section with an undercut angle of about 90. Such a second STI region can be fabricated using a porous surface section formed in an upper surface of the collector region.

US Patent:

7378324, May 27, 2008

Filed:

Mar 30, 2006

Appl. No.:

11/308503

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Rajendran Krishnasamy - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/331

US Classification:

438350, 438321, 438363, 438372, 257E21379

Abstract:

Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.

US Patent:

7485539, Feb 3, 2009

Filed:

Jan 13, 2006

Appl. No.:

11/332564

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Joel P. de Souza - Putnam Valley NY, US
Keith E. Fogel - Hopewell Junction NY, US
Alexander Reznicek - Mount Kisco NY, US
Devendra K. Sadana - Pleasantville NY, US
Ghavam Shahidi - Pound Ridge NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/76

US Classification:

438370, 438413, 438416, 438423, 257E21561, 257E21563

Abstract:

A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

US Patent:

7511317, Mar 31, 2009

Filed:

Jun 9, 2006

Appl. No.:

11/423286

Inventors:

Thomas N. Adam - Poughkeepsie NY, US
Stephen W. Bedell - Wappingers Falls NY, US
Joel P. de Souza - Putnam Valley NY, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Thomas A. Wallner - Pleasant Valley NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/082
H01L 27/102

US Classification:

257197, 257565

Abstract:

A method of forming an isolation region using porous silicon and a related structure are disclosed. One embodiment of the method may include forming a collector region; forming a porous silicon region in the collector region; forming a crystalline silicon intrinsic base layer over the collector region, the intrinsic base layer extending over a portion of the porous silicon region to form an extrinsic base; and forming an isolation region in the porous silicon region. The method is applicable to forming an HBT having a structure including a crystalline silicon intrinsic base extending beyond a collector region and extending over an isolation region to form a continuous intrinsic-to-extrinsic base conduction path of low resistance. The HBT has improved performance by having a smaller collector to intrinsic base interface and larger intrinsic base to extrinsic base interface.