Thomas M Armstead

US Patent:

7428483, Sep 23, 2008

Filed:

Jun 16, 2005

Appl. No.:

11/154905

Inventors:

Thomas Michael Armstead - Rochester MN, US
Gregory Albert Dancker - Rochester MN, US
Paul Emery Schardt - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 11/00

US Classification:

703 14, 714 41

Abstract:

A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

US Patent:

7533011, May 12, 2009

Filed:

May 21, 2008

Appl. No.:

12/124520

Inventors:

Thomas Michael Armstead - Rochester MN, US
Gregory Albert Dancker - Rochester MN, US
Paul Emery Schardt - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50
G06F 11/00

US Classification:

703 15, 714 41

Abstract:

A simulation system includes glitch injection circuitry in one or more hardware design units to allow the injection of glitches or noise to evaluate the system's response to errors on signals between the hardware design units. The simulation system includes a stimulation module with a set of drivers to input simulation patterns into the design units. Some inputs to software models are driven by the outputs of software models of another design unit. The stimulation module can monitor these signals driven by the software model but it is difficult for the stimulation module to directly drive these signals. The added glitch circuitry allows injection of errors into the simulated hardware by the stimulation module on signals that are not directly driven by the stimulation module but are driven by the outputs of hardware design units.

US Patent:

7747414, Jun 29, 2010

Filed:

Nov 29, 2007

Appl. No.:

11/947636

Inventors:

Thomas M. Armstead - Rochester MN, US
Lance R. Meyer - Rochester MN, US
Paul E. Schardt - Rochester MN, US
Robert A. Shearer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/30

US Classification:

702186

Abstract:

A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

US Patent:

20070005852, Jan 4, 2007

Filed:

Jun 30, 2005

Appl. No.:

11/173286

Inventors:

Thomas Armstead - Rochester MN, US
Eldon Nelson - Rochester MN, US
Paul Schardt - Rochester MN, US
Corey Swenson - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13/00

US Classification:

710100000

Abstract:

Methods, apparatus, and articles of manufacture that allow packet-based communication transactions between devices over an interconnect bus to be captured in a standardized format are provided. The standardized format may enable the display of the bus transactions via a graphical user interface (GUI), which may greatly facilitate viewing and analyzing the transactions when validating communications.

US Patent:

20070093986, Apr 26, 2007

Filed:

Oct 26, 2005

Appl. No.:

11/259294

Inventors:

Thomas Armstead - Rochester MN, US
Lance Meyer - Rochester MN, US
Paul Schardt - Rochester MN, US
Robert Shearer - Rochester MN, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15/00

US Classification:

702182000

Abstract:

A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

US Patent:

20080133489, Jun 5, 2008

Filed:

Jan 23, 2008

Appl. No.:

12/018329

Inventors:

Thomas M. Armstead - Rochester MN, US
Lance R. Meyer - Rochester MN, US
Paul E. Schardt - Rochester MN, US
Robert A. Shearer - Rochester MN, US

International Classification:

G06F 7/10
G06F 17/30

US Classification:

707 3, 707E17014

Abstract:

A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

US Patent:

20090037165, Feb 5, 2009

Filed:

Jul 30, 2007

Appl. No.:

11/830147

Inventors:

Thomas Michael Armstead - Rochester MN, US
John Hubert Klaus - Rochester MN, US
Paul Emery Schardt - Rochester MN, US
Scott Michael Willenborg - Stewartville MN, US

International Classification:

G06F 9/45

US Classification:

703 22

Abstract:

A method, article of manufacture and apparatus for simulating a plurality of transactions. A first group of transactions with first simulation properties are provided and a second group of transactions with second simulation properties are provided. The first simulation properties are different from the second simulation properties. During software simulation of a hardware model, the first group of transactions and the second group of transactions are issued to the hardware model. The first group of transactions and the second group of transactions are processed using the hardware model. At least a portion of the first group of transactions and the second group of transactions is processed simultaneously using the hardware model. The first simulation properties are used to process the first group of transactions using the hardware model and wherein the second simulation properties are used to process the second group of transactions using the hardware model.