Thomas C Boyd

US Patent:

20130270691, Oct 17, 2013

Filed:

Dec 16, 2011

Appl. No.:

13/976098

Inventors:

Debendra Mallik - Chandler AZ, US
Sridhar Narasimhan - Chandler AZ, US
Mathew J. Manusharow - Phoenix AZ, US
Thomas A. Boyd - North Plains OR, US

International Classification:

H01L 23/34
H01L 21/50

US Classification:

257713, 438122

Abstract:

A package for a microelectronic die () includes a first substrate () adjacent to a first surface () of the die, a second substrate () adjacent to the first substrate, and a heat spreader () adjacent to a second surface () of the die. The heat spreader makes contact with both the first substrate and the second substrate.

US Patent:

20170179066, Jun 22, 2017

Filed:

Dec 18, 2015

Appl. No.:

14/974881

Inventors:

Russell S. Aoki - Tacoma WA, US
John W. Jaeger - Olympia WA, US
Michael S. Brazel - Fedeal Way WA, US
Daniel P. Carter - Bainbridge Island WA, US
Anthony P. Valpiani - Olympia WA, US
Michael R. Hui - Seattle WA, US
Rashelle Yee - Dupont WA, US
Joseph J. Jasniewski - Olympia WA, US
Shelby A. Ferguson - Lacey WA, US
Thomas A. Boyd - North Plains OR, US
Jonathan W. Thibado - Beaverton OR, US
Penny K. Woodcock - Beaverton OR, US
Rachel G. Taylor - Dupont WA, US
Laura S. Mortimer - Lacey WA, US

International Classification:

H01L 23/00
B23K 3/02

Abstract:

Reflow Grid Array technology may be implemented on an interposer device, where the interposer is placed between a motherboard and a BGA package. The interposer may provide a controlled heat source to reflow solder between the interposer and the BGA package. A technical problem faced by an interposer using RGA technology is solder cleaning and removal when removing a BGA package. Technical solutions described herein provide processes and equipment for bulk solder removal from a BGA package that can be executed in the field.

US Patent:

20170179067, Jun 22, 2017

Filed:

Dec 18, 2015

Appl. No.:

14/975532

Inventors:

- Santa Clara CA, US
MICHAEL R. HUI - Tacoma WA, US
JONATHON R. CARSTENS - Lacey WA, US
MICHAEL S. BRAZEL - Federal Way WA, US
DANIEL P. CARTER - Olympia WA, US
THOMAS A. BOYD - North Plains OR, US
SHELBY A. FERGUSON - Lacey WA, US
RASHELLE YEE - Puyallup WA, US
JOSEPH J. JASNIEWSKI - Olympia WA, US
HARVEY R. KOFSTAD - Vernonia OR, US
ANTHONY P. VALPIANI - Olympia WA, US

International Classification:

H01L 23/00
B23K 3/08
B23K 1/00

Abstract:

Embodiments of the present disclosure describe package alignment frames for a local reflow process to attach a semiconductor package to an interposer. The frame may comprise a two frame system. The interposer may be on a mounting table or on a circuit board. The frame may include a body with a rectangular opening dimensioned to receive a semiconductor package to be coupled to the interposer. The frame may be to align a ball grid array of the semiconductor package with pads of the interposer. A second frame may be to receive the first frame and may be to align a ball grid array of the interposer with pads of the circuit board. A single frame may be used to couple a semiconductor package to an interposer and to couple the interposer to a circuit board. Other embodiments may be described and/or claimed.