Thomas W Bucht

US Patent:

6922391, Jul 26, 2005

Filed:

Nov 7, 2000

Appl. No.:

09/707443

Inventors:

Steve King - Portland OR, US
Chiayin Mao - Beaverton OR, US
Thomas W. Bucht - Hillsboro OR, US

Assignee:

Crossroads Systems Inc. - Austin TX

International Classification:

H04L012/26

US Classification:

370229, 370359, 370360, 370386, 3703951, 370449

Abstract:

A method for decreasing routing latency of a switching platform comprises identifying ports which have changed their operational state and modifying the port polling code associated with the respective ports so that operational ports are polled for frames to be routed, while non-operational ports are not polled. In one embodiment, the method is implemented in a fibre channel switch. Non-operational ports are identified as having operational states below a pre-determined threshold level of functionality. The polling code for the ports is modified while polling operations are carried out in the switch. The code for a newly operational port is modified by copying into the code one or more instructions that poll the port for a frame and routes the frame. The code for a newly non-operational port is modified by copying into the code a branch instruction that bypasses the remainder of the polling code for the port. The frame routing latency of the switch is reduced because ports which are non-operational and will not produce frames are not polled.

US Patent:

6977897, Dec 20, 2005

Filed:

Oct 24, 2000

Appl. No.:

09/695754

Inventors:

Michael A. Nelson - Portland OR, US
Thomas W. Bucht - Hillsboro OR, US

Assignee:

Crossroads Systems, Inc. - Austin TX

International Classification:

H04L012/42
G06F013/00

US Classification:

370235, 370258, 375372, 710 53, 710 56

Abstract:

A system and method for compensating for differences between a recovered receive clock and an internal transmit clock in an elastic buffer and thereby preventing corruption of data. In one embodiment, the system comprises a circularly accessed buffer coupled to read and write logic. The read and write logic read and write to locations within the circular buffer as indicated by respective read and write pointers. The system further comprises control logic which compares the pointers to determine whether the buffer is approaching an underflow or overflow condition and adds or deletes fill words between frames of data to compensate for the underflow or overflow condition. In one embodiment, the system includes fill word logic which is configured to add a fill word bit to each received word and to set or clear the fill word bit to indicate whether or not the corresponding word is a fill word.

US Patent:

7333489, Feb 19, 2008

Filed:

Oct 24, 2000

Appl. No.:

09/695755

Inventors:

Michael A. Nelson - Portland OR, US
Thomas W. Bucht - Hillsboro OR, US

Assignee:

Crossroads Systems, Inc. - Austin TX

International Classification:

H04L 12/28
H04L 12/56

US Classification:

370392, 370412

Abstract:

A system and method for storing header information in parallel with corresponding frames of data, wherein the frames of data are stored in a first-in-first-out buffer and wherein the header information is accessed to make routing decisions for the frames of data while avoiding having to read the frames out of the buffer. In one embodiment, this buffer system is implemented in a port of a network switch. Receive logic in the port stores frames of data in the storage elements of a FIFO buffer and concurrently snoops on the frame data to obtain header information. The header information is stored in a buffer separate from the FIFO that stores the frames. The header information can be read from the header buffer rather than the frame buffer. A routing decision for each frame can be made before a previous frame is completely read out of the frame FIFO, hence before the corresponding frame is ready to be transmitted. A timer may also be associated with each header in the header buffer so that it can be determined when frames are stale and must be discarded.

US Patent:

7508756, Mar 24, 2009

Filed:

Mar 28, 2005

Appl. No.:

11/091151

Inventors:

Steve King - Portland OR, US
Chiayin Mao - Beaverton OR, US
Thomas W. Bucht - Hillsboro OR, US

Assignee:

Crossroads Systems, Inc. - Austin TX

International Classification:

H04L 12/26

US Classification:

370229, 370359, 370360, 370386, 3703951, 370449

Abstract:

A method for decreasing routing latency of a switching platform comprises identifying ports which have changed their operational state and modifying the port polling code associated with the respective ports so that operational ports are polled for frames to be routed, while non-operational ports are not polled. In one embodiment, the method is implemented in a fiber channel switch. Non-operational ports are identified as having operational states below a pre-determined threshold level of functionality. The polling code for the ports is modified while polling operations are carried out in the switch. The code for a newly operational port is modified by copying into the code one or more instructions that poll the port for a frame and routes the frame. The code for a newly non-operational port is modified by copying into the code a branch instruction that bypasses the remainder of the polling code for the port. The frame routing latency of the switch is reduced because ports which are non-operational and will not produce frames are not polled.

US Patent:

7912053, Mar 22, 2011

Filed:

Mar 23, 2009

Appl. No.:

12/409331

Inventors:

Steve King - Portland OR, US
Chiayin Mao - Beaverton OR, US
Thomas W. Bucht - Hillsboro OR, US

Assignee:

Crossroads Systems, Inc. - Austin TX

International Classification:

H04L 12/28

US Classification:

370389

Abstract:

A method for decreasing routing latency of a switching platform comprises identifying ports which have changed their operational state and modifying the port polling code associated with the respective ports so that operational ports are polled for frames to be routed, while non-operational ports are not polled. In one embodiment, the method is implemented in a fiber channel switch. Non-operational ports are identified as having operational states below a pre-determined threshold level of functionality. The polling code for the ports is modified while polling operations are carried out in the switch. The code for a newly operational port is modified by copying into the code one or more instructions that poll the port for a frame and routes the frame. The code for a newly non-operational port is modified by copying into the code a branch instruction that bypasses the remainder of the polling code for the port. The frame routing latency of the switch is reduced because ports which are non-operational and will not produce frames are not polled.

US Patent:

20020004866, Jan 10, 2002

Filed:

May 8, 2001

Appl. No.:

09/851594

Inventors:

Thomas Bucht - Hillsboro OR, US

International Classification:

G06F013/00

US Classification:

710/107000

Abstract:

An apparatus for reducing CPU latency by reducing CPU bus read/write cycles, the apparatus includes a hardware register capable of testing data for one or more validity bits. A CPU is in communication with the hardware register during a first bus cycle and the CPU directs the hardware register to drive the data substantially simultaneously to the CPU and a second register. The data validity signal is performed in close proximity to the data transfer to the CPU and the second hardware device and the validity signal is forwarded to the second register without a subsequent bus cycle instruction to the second register from the CPU.

US Patent:

6392570, May 21, 2002

Filed:

Sep 14, 2000

Appl. No.:

09/662075

Inventors:

Thomas W. Bucht - Hillsboro OR

Assignee:

Crossroads Systems, Inc. - Austin TX

International Classification:

H03M 700

US Classification:

341 59

Abstract:

A method and system for decoding 8B/10B data is provided. In one embodiment, the method includes the steps of determining the presence of one of a plurality of predetermined data sequences within a first portion of a data word, translating the predetermined data sequences into representative signals (flags) having a smaller aggregate data width than the first portion of the data word, and providing the representative signals together with remaining portions of the data word to a logic block for decoding. This embodiment of the present method allows the encoded data to be decoded using limited-width decoders, allows first and second portions of each encoded data word to be decoded concurrently, and allows the decoding of the encoded data words to be pipelined to increase the throughput of the decoder.