Thomas E Byrd

US Patent:

20100232121, Sep 16, 2010

Filed:

Aug 29, 2008

Appl. No.:

12/675488

Inventors:

Glen C. Oliver - Arlington TX, US
Thomas E. Byrd - Grand Prairie TX, US
Alan L. Phillips - Burleson TX, US
Charles Donald Dupriest - Arlington TX, US
Samuel O. Polk - Arlington TX, US

International Classification:

H05K 1/14
H05K 1/18
H05K 3/00

US Classification:

361749, 174260, 29829

Abstract:

A printed board includes a base printed board including a trace; an electronic component operably associated with the base printed board; and a dielectric connector build-up extending from the base printed board. The dielectric connector build-up defines a via. The printed board further includes a land attachment site disposed in the via. The land attachment site extends through the dielectric connector build-up and into the base printed board. The land attachment site is electrically coupled with the trace and is configured to be electrically coupled to another printed board by one of an electrically conductive compound and a flowed solder ball.

US Patent:

20140152373, Jun 5, 2014

Filed:

Dec 3, 2013

Appl. No.:

14/094977

Inventors:

- Bethesda MD, US
David L. Hoelscher - Arlington TX, US
Thomas Eugene Byrd - Grand Prairie TX, US

Assignee:

LOCKHEED MARTIN CORPORATION - Bethesda MD

International Classification:

H03K 17/04

US Classification:

327374

Abstract:

Power modules with reduced parasitic inductances are provided. A power module includes a first substrate including a first electrically-conductive layer and a second substrate including a second electrically-conductive layer. These substrates may be stacked on each other. A scalable network of power switches may be arranged on the substrates. Power bars may be connectable to the electrically-conductive layers through electromechanical interfaces at selectable interface locations. The locations and/or type of interface may be selectable based on the arrangement of the switches. The first and second electrically-conductive layers may be disposed on mutually opposed surfaces of a dielectric layer having a thickness chosen to effect a level of coupling between respective source and return current paths provided by the electrically-conductive layers. The level of coupling may be arranged to increase the mutual inductance within the power module, which can effectively reduce the formation of parasitic inductance in the power module.