Thomas C Chen

US Patent:

20170286827, Oct 5, 2017

Filed:

Apr 1, 2016

Appl. No.:

15/088543

Inventors:

GREGORY K. CHEN - Hillsboro OR, US
JAE-SUN SEO - Tempe AZ, US
THOMAS C CHEN - Ann Arbor MI, US
RAGHAVAN KUMAR - Hillsboro OR, US

International Classification:

G06N 3/063
G06N 3/04

Abstract:

An apparatus and method are described for a neuromorphic processor design in which neuron timing information is duplicated on a neuromorphic core. For example, one embodiment of an apparatus comprises: a first neurosynaptic core comprising a plurality of neurons and a synapse array comprising a plurality of synapses to communicatively couple the plurality of neurons, each synapse connecting two neurons having a weight associated therewith, wherein a first neuron is to generate an output spike based on the weights of synapses over which inputs are received from the other neurons; a second neurosynaptic core also comprising a plurality of neurons and having at least one counter to maintain a count value indicative of spike timing for a second neuron, wherein a spike output of the second neuron in the second neurosynaptic core is communicatively coupled over a first synapse to the first neuron in the first neurosynaptic core; and a duplicate counter maintained within the first neurosynaptic core and synchronized with the counter from the second neurosynaptic core, the first neuron to use a first value from the duplicate counter to adjust the weight of the first synapse coupling the second neuron to the first neuron.